公开(公告)号：US10985316B2

公开(公告)日：2021-04-20

申请号：US16359092

申请日：2019-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang Chen ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Wen-Ting Chu ,  Pili Huang ,  Cheng-Jun Wu

IPC: H01L27/088 ,  H01L21/8236 ,  H01L45/00 ,  H01L27/24

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnect layers arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnect layers. A lower surface of the bottom electrode includes a material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. A reactivity reducing layer contacts the lower surface of the bottom electrode. The reactivity reducing layer has a second electronegativity that is greater than or equal to the first electronegativity.