公开(公告)号：US10325949B2

公开(公告)日：2019-06-18

申请号：US16055308

申请日：2018-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Chang ,  Sheng-Chan Li ,  Cheng-Hsien Chou ,  Tsung-Wei Huang ,  Min-Hui Lin ,  Yi-Ming Lin

IPC: H01L21/02 ,  H01L27/146 ,  H01L21/3105

Abstract: An image sensor device is provided. The image sensor device includes a substrate having a first surface, a second surface, and a light-sensing region. The image sensor device includes a first isolation structure in the substrate and adjacent to the first surface. The first isolation structure surrounds the light-sensing region. The image sensor device includes a second isolation structure passing through the first isolation structure and the substrate under the first isolation structure. The second isolation structure surrounds the light-sensing region and a portion of the first isolation structure.

公开(公告)号：US20190115382A1

公开(公告)日：2019-04-18

申请号：US16218806

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Wen-I Hsu ,  Tsun-Kai Tsao ,  Chih-Yu Lai ,  Jiech-Fun Lu ,  Yeur-Luen Tu

IPC: H01L27/146 ,  H01L31/18

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate having a first photodetector region and forming a gate material over the gate dielectric layer. A dielectric protection layer is deposited over the gate dielectric layer and a first sidewall spacer is formed along a side of the gate material. The dielectric protection layer extends from a first location directly over the first photodetector region to a second location between the first sidewall spacer and the gate dielectric layer.

公开(公告)号：US09960200B1

公开(公告)日：2018-05-01

申请号：US15337328

申请日：2016-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Sheng-Chau Chen ,  Cheng-Yuan Tsai ,  Chih-Hui Huang

IPC: H01L31/0232 ,  H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/14625 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689

Abstract: The present application relates to a method to simplify the scribe line opening filling processes, and to further improve the surface uniformity of the conductive pad fabrication process. A passivation layer is formed over a semiconductor substrate, and a scribe line opening is formed through the passivation layer and the semiconductor substrate. To fill the scribe line opening, a first dielectric layer is formed within the scribe line opening over the conductive pad and extending over the passivation layer. The first dielectric layer is formed by a selective deposition process such that the first dielectric layer is formed on the conductive pad at a deposition rate greater than that formed on the passivation layer.

公开(公告)号：US09859323B1

公开(公告)日：2018-01-02

申请号：US15180395

申请日：2016-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Sheng-Chan Li ,  Zhi-Yang Wang

IPC: H01L31/062 ,  H01L31/113 ,  H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689

Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor having a passivation layer is provided. The CMOS image sensor includes a sensing device substrate. Isolation structures are positioned within trenches of the sensing device substrate. The isolation structures are arranged along opposing sides of a plurality of image sensing devices. The CMOS image sensor also includes a passivation layer. The passivation layer includes passivation sidewalls arranged along the sidewalls of the isolation structures. A metallic grid overlies the passivation layer. The metallic grid includes a metal framework surrounding openings overlying the plurality of image sensing devices. The passivation layer further includes passivation section underlying the openings.

公开(公告)号：US20170243915A1

公开(公告)日：2017-08-24

申请号：US15591722

申请日：2017-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Shih Pei Chou ,  Chih-Yu Lai ,  Sheng-Chau Chen ,  Chih-Ta Chen ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L21/823878 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14687 ,  H01L33/20

Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.

公开(公告)号：US20220362903A1

公开(公告)日：2022-11-17

申请号：US17317968

申请日：2021-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Lung Lin ,  Kuo-Ming Wu ,  Cheng-Hsien Chou ,  I-Nan Chen ,  Sheng-Chau Chen ,  Cheng-Yuan Tsai

IPC: B24B37/14 ,  B24B37/10

Abstract: Various embodiments of the present disclosure are directed towards a chemical mechanical polishing (CMP) system including a first CMP head and a second CMP head. The first CMP head is configured to retain a workpiece and comprises a first plurality of pressure elements disposed across a first pressure control plate. The second CMP head is configured to retain the workpiece. The second CMP head comprises a second plurality of pressure elements disposed across a second pressure control plate. A distribution of the first plurality of pressure elements across the first pressure control plate is different from a distribution of the second plurality of pressure elements across the second pressure control plate.

公开(公告)号：US20200321251A1

公开(公告)日：2020-10-08

申请号：US16908966

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Chih-Hui Huang ,  Kuo-Ming Wu

IPC: H01L21/822 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.

公开(公告)号：US20200075657A1

公开(公告)日：2020-03-05

申请号：US16121958

申请日：2018-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hui Huang ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Kuo-Ming Wu ,  Sheng-Chan Li

IPC: H01L27/146

Abstract: Various embodiments of the present application are directed towards an image sensor having a reflector. In some embodiments, the image sensor comprises a substrate, an interlayer dielectric (ILD) structure, an etch stop layer, a wire, and the reflector. The substrate comprises a photodetector. The ILD structure is over the substrate, and the etch stop layer is over the ILD structure. The wire is in the etch stop layer. The reflector is directly over the photodetector and is in the etch stop layer. An upper surface of the wire is elevated above an upper surface of the reflector. By forming the reflector directly over the photodetector, the reflector may reflect radiation that passes through the photodetector without being absorbed back to the photodetector. This gives the photodetector a second chance to absorb the radiation and enhances the quantum efficiency (QE) of the photodetector.

公开(公告)号：US10043841B1

公开(公告)日：2018-08-07

申请号：US15663985

申请日：2017-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Chang ,  Sheng-Chan Li ,  Cheng-Hsien Chou ,  Tsung-Wei Huang ,  Min-Hui Lin ,  Yi-Ming Lin

IPC: H01L21/00 ,  H01L27/146 ,  H01L21/02 ,  H01L21/3105

Abstract: A method for forming an image sensor device is provided. The method includes providing a substrate having a front surface and a back surface. The method includes removing a first portion of the substrate to form a first trench. The method includes forming a first isolation structure in the first trench. The first isolation structure has a top surface. The method includes removing a second portion of the first isolation structure and a third portion of the substrate to form a second trench passing through the first isolation structure and extending into the substrate. The method includes forming a second isolation structure in the second trench. The method includes forming a light-sensing region in the substrate. The method includes removing a fourth portion of the substrate to expose a first bottom portion of the second isolation structure and a backside of the light-sensing region.

公开(公告)号：US09917003B2

公开(公告)日：2018-03-13

申请号：US13930189

申请日：2013-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Cheng-Hsien Chou ,  Hung-Ling Shih ,  Tsun-Kai Tsao ,  Ming-Huei Shen ,  Kuo-Hwa Tzeng ,  Yeur-Luen Tu

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211

Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a bottom portion and a top portion. The bottom portion has a lining oxide layer, a negatively-charged liner and a first silicon oxide. The lining oxide layer is peripherally enclosed by the semiconductor substrate, the negatively-charged liner is peripherally enclosed by the lining oxide layer, and the first silicon oxide is peripherally enclosed by the negatively-charged liner. The top portion adjoins the bottom portion, and has a second silicon oxide peripherally enclosed by and contacting the semiconductor substrate.