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    Package heat dissipation including a die attach film
    12.
    发明授权
    Package heat dissipation including a die attach film 有权

    公开(公告)号：US12199008B2

    公开(公告)日：2025-01-14

    申请号：US17219602

    申请日：2021-03-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jaimal Mallory Williamson ,  Rongwei Zhang

    IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31

    Abstract: In examples, a semiconductor package comprises a substrate including a conductive layer; a conductive pillar coupled to the conductive layer; and a semiconductor die having first and second opposing surfaces. The first surface is coupled to the conductive pillar. The package also includes a die attach film abutting the second surface of the semiconductor die and a metal layer abutting the die attach film and having a metal layer surface facing away from the die attach film. The metal layer surface is exposed to an exterior of the FCCSP. The package includes a mold compound layer covering the substrate.

    PACKAGE SUBSTRATE HAVING POROUS DIELECTRIC LAYER
    14.
    发明申请
    PACKAGE SUBSTRATE HAVING POROUS DIELECTRIC LAYER 有权

    公开(公告)号：US20230118218A1

    公开(公告)日：2023-04-20

    申请号：US17506156

    申请日：2021-10-20

    Applicant: Texas Instruments Incorporated

    Inventor： Jaimal Mallory Williamson

    IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48

    Abstract: A multilayer package substrate includes a plurality of dielectric layers including a top dielectric layer on a top side and a bottom dielectric layer on a bottom side. A top patterned metal layer is on the top dielectric layer and a bottom patterned metal layer is on the bottom dielectric layer. At least one of the top dielectric layer and the bottom dielectric layer is a porous dielectric layer having a plurality of pores including an average porosity of at least 5% averaged over its thickness.

    Via integrity and board level reliability testing
    15.
    发明授权
    Via integrity and board level reliability testing 有权

    公开(公告)号：US11081406B2

    公开(公告)日：2021-08-03

    申请号：US16015965

    申请日：2018-06-22

    Applicant: Texas Instruments Incorporated

    Inventor： Jaimal Mallory Williamson ,  Ethan Tilden Davis

    IPC: H01L21/66 ,  H01L21/48 ,  G01R31/28 ,  H01L23/498

    Abstract: Described examples provide a method to evaluate reliability of ball grid array products in which an interconnect stress test is performed that passes current through outer layer micro-vias of a test coupon portion of a production panel that is soldered to a printed circuit board, and the reliability of ball grid array products manufactured using package substrate portions of the production panel is evaluated according to the results of the interconnect stress test. A test coupon includes a rigid core material layer, dielectric layers laminated between copper layers above and below the core material layer, conductive micro-vias that extend through at least one of the dielectric layers between two of the copper layers, and conductive land pads on an outer one of the dielectric layers, the conductive land pads individually contacting one of the micro-vias.

    PACKAGE SUBSTRATE WITH PARTIALLY RECESSED CAPACITOR
    16.
    发明申请
    PACKAGE SUBSTRATE WITH PARTIALLY RECESSED CAPACITOR 审中-公开

    公开(公告)号：US20200294899A1

    公开(公告)日：2020-09-17

    申请号：US16795873

    申请日：2020-02-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jaimal Mallory Williamson ,  Snehamay Sinha

    IPC: H01L23/498 ,  H01L23/64 ,  H01L23/00 ,  H01L21/48

    Abstract: A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.

    PACKAGE SUBSTRATE WITH CTE MATCHING BARRIER RING AROUND MICROVIAS
    18.
    发明申请
    PACKAGE SUBSTRATE WITH CTE MATCHING BARRIER RING AROUND MICROVIAS 有权

    公开(公告)号：US20220254735A1

    公开(公告)日：2022-08-11

    申请号：US17679082

    申请日：2022-02-24

    Applicant: Texas Instruments Incorporated

    Inventor： Jaimal Mallory Williamson ,  Guangxu Li

    IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

    Abstract: A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

    Package substrate with partially recessed capacitor
    19.
    发明授权
    Package substrate with partially recessed capacitor 有权

    公开(公告)号：US11289412B2

    公开(公告)日：2022-03-29

    申请号：US16795873

    申请日：2020-02-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jaimal Mallory Williamson ,  Snehamay Sinha

    IPC: H01L23/498 ,  H01L23/64 ,  H01L23/00 ,  H01L21/48 ,  H01L23/48

    Abstract: A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.

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