公开(公告)号：US20200327950A1

公开(公告)日：2020-10-15

申请号：US16916911

申请日：2020-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind GANESAN ,  Jaiganesh BALAKRISHNAN ,  Nagarajan VISWANATHAN ,  Yeswanth GUNTUPALLI ,  Ajai PAULOSE ,  Mathews JOHN ,  Jagannathan VENKATARAMAN ,  Neeraj SHRIVASTAVA

IPC: G11C29/02 ,  G11C17/18 ,  G11C17/16 ,  G11C17/14

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

公开(公告)号：US20200152284A1

公开(公告)日：2020-05-14

申请号：US16235698

申请日：2018-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind GANESAN ,  Jaiganesh BALAKRISHNAN ,  Nagarajan VISWANATHAN ,  Yeswanth GUNTUPALLI ,  Ajai PAULOSE ,  Mathews JOHN ,  Jagannathan VENKATARAMAN ,  Neeraj SHRIVASTAVA

IPC: G11C29/02 ,  G11C17/18 ,  G11C17/14 ,  G11C17/16

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

公开(公告)号：US20170245803A1

公开(公告)日：2017-08-31

申请号：US15298764

申请日：2016-10-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hussam AHMED ,  Jagannathan VENKATARAMAN ,  Sandeep Kesrimal OSWAL ,  Antoine Lourdes Praveen AROUL ,  Hari Babu TIPPANA ,  Anand Hariraj UDUPA

IPC: A61B5/00 ,  A61B5/0205 ,  A61B5/1455

CPC classification number: A61B5/7225 ,  A61B5/02416 ,  A61B5/681 ,  A61B5/7203 ,  A61B2560/0247

Abstract: A bio-sensing device (and method) calibrates a time period used to make bio-physical measurements. The device initiates a light source sense phase followed by a first ambient sense phase and a second ambient sense phase. In the light source sense phase, the device is configured to receive a digital value indicative of current through a photodetector while the light source circuit is enabled and in each of the first and second ambient sense phases, the device is configured to receive digital values while the light source circuit is disabled. The device iteratively varies the time period between the phases until the digital value received during the first ambient sense phase is within a threshold of the digital value received during the second ambient sense phase. It then applies the same time separation between the light source sense phase and the ambient phase thereby equalizing the magnitude of the ambient light in the two phases.

公开(公告)号：US20220197330A1

公开(公告)日：2022-06-23

申请号：US17245711

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Ani XAVIER ,  Jagannathan VENKATARAMAN ,  Raviteja VELISETTI

IPC: G06F1/10 ,  H03L7/081

Abstract: A first logic gate has a first input coupled to a first circuit input or a second circuit input, a second input selectively coupled to a third circuit input or a fourth circuit input, and a first output. The first output has a signal with a duty cycle that is a function of a phase difference between a first signal on the first input and a second signal on the second input. A second logic gate has a third input coupled to the third circuit input or the fourth circuit input, a fourth input coupled to the second circuit input or the fourth circuit input, and a second output. The second output has a signal with a duty cycle that is a function of a phase difference between a third signal on the third input and a fourth signal on the fourth input.

公开(公告)号：US20220190856A1

公开(公告)日：2022-06-16

申请号：US17689627

申请日：2022-03-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sarma Sundareswara GUNTURI ,  Jagannathan VENKATARAMAN ,  Jawaharlal TANGUDU ,  Narasimhan RAJAGOPAL ,  Eeshan MIGLANI

IPC: H04B1/10 ,  H04B1/40 ,  H03G3/30 ,  H04B1/12

Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.

公开(公告)号：US20210175914A1

公开(公告)日：2021-06-10

申请号：US17112137

申请日：2020-12-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sarma Sundareswara GUNTURI ,  Jagannathan VENKATARAMAN ,  Jawaharlal TANGUDU ,  Narasimhan RAJAGOPAL ,  Eeshan MIGLANI

IPC: H04B1/10 ,  H04B1/40 ,  H04B1/12 ,  H03G3/30

Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.

公开(公告)号：US20200228127A1

公开(公告)日：2020-07-16

申请号：US16828149

申请日：2020-03-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raja Reddy PATUKURI ,  Jagannathan VENKATARAMAN ,  Shagun DUSAD

IPC: H03M1/08 ,  H04B1/40 ,  H03M1/10

Abstract: A transceiver system includes a clock generator and an analog-to-digital circuit (ADC). The transceiver system also includes a coupling correction circuit coupled to the clock generator and to the ADC, wherein the coupling correction circuit is configured to provide an in-phase correction and a quadrature-phase correction to a signal received by the ADC.

公开(公告)号：US20200177130A1

公开(公告)日：2020-06-04

申请号：US16274519

申请日：2019-02-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rahul SHARMA ,  Jagannathan VENKATARAMAN ,  Eeshan MIGLANI ,  Sandeep Kesrimal OSWAL

IPC: H03C1/06 ,  H03C1/60 ,  H04B1/04

Abstract: A system includes a Zero IF transmitter having a mixer and a programmable gain stage. The Zero IF transmitter also includes an intermediate stage between the mixer and the programmable gain stage, wherein the intermediate stage is configured to decouple the mixer and the programmable gain stage.

公开(公告)号：US20190097644A1

公开(公告)日：2019-03-28

申请号：US16204349

申请日：2018-11-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jagannathan VENKATARAMAN ,  Eeshan MIGLANI

IPC: H03M1/08

CPC classification number: H03M1/08 ,  H03K17/162 ,  H03K17/165 ,  H03M1/742

Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.