公开(公告)号：US20240371780A1

公开(公告)日：2024-11-07

申请号：US18142888

申请日：2023-05-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Hsien Huang ,  Jun He ,  Yinlung Lu ,  Yao-Chun Chuang

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor device with a multi-tier construction includes a first tier having a first die, a second die spaced apart from the first die in a first direction and a fill material therebetween. A second tier overlays the first tier, and includes a bridge die partially overlaying the fill material and the first and second dies. The bridge die provides an electrical interconnection between the first and second dies in the first tier. The device also has a first protective structure aligned with a first interface between an end of the first die and the fill material that includes a first part formed on a first side of the first die at the end of the first die; and a second part formed on a first side of the bridge die. The first and second parts are aligned and form the first protective structure, mitigating cracking near the bridge die.

公开(公告)号：US20240038701A1

公开(公告)日：2024-02-01

申请号：US17814836

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Ting Kuo ,  Li-Hsien Huang ,  Tien-Chung Yang ,  Yao-Chun Chuang ,  Yinlung Lu ,  Jun He

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L24/08 ,  H01L23/5389 ,  H01L23/49816 ,  H01L23/3128 ,  H01L23/5286 ,  H01L23/5226 ,  H01L24/14 ,  H01L24/19 ,  H01L24/73 ,  H01L2224/12105 ,  H01L2924/15311 ,  H01L2224/02379

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes: a die having a frontside and a backside; a first redistribution layer (RDL) structure disposed on the backside of the die; a second RDL structure disposed on and electrically connected to the frontside of the die; a through integrated fan-out via (TIV) disposed lateral to the die and extending to electrically connect the first and the second RDL structures; a molding compound disposed between the first and second RDL structures; an enhancement layer disposed on the second RDL structure; a plurality of pre-solder bumps; and a plurality of solder balls disposed on and electrically connected to the second RDL structure. The enhancement layer includes a plurality of cascaded openings electrically connected to the first RDL structure. Each of the pre-solder bumps is disposed in one of the cascaded openings.

公开(公告)号：US11630149B2

公开(公告)日：2023-04-18

申请号：US17353543

申请日：2021-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jun He ,  Yu-Ting Lin ,  Wei-Hsun Lin ,  Yung-Liang Kuo ,  Yinlung Lu

IPC: G01R31/28

Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.

公开(公告)号：US11448692B2

公开(公告)日：2022-09-20

申请号：US17198764

申请日：2021-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jun He ,  Yu-Ting Lin ,  Wei-Hsun Lin ,  Yung-Liang Kuo ,  Yinlung Lu

IPC: G01R31/28 ,  G01R31/26

Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.

公开(公告)号：US11073551B2

公开(公告)日：2021-07-27

申请号：US16522551

申请日：2019-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jun He ,  Yu-Ting Lin ,  Wei-Hsun Lin ,  Yung-Liang Kuo ,  Yinlung Lu

IPC: G01R31/28

Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.