公开(公告)号：US20150043279A1

公开(公告)日：2015-02-12

申请号：US14387908

申请日：2013-02-14

申请人： Sharp Kabushiki Kaisha

发明人： Yoshimitsu Yamauchi

IPC分类号： H01L27/115 ,  G11C16/10 ,  H01L29/786 ,  G11C16/04

CPC分类号： H01L27/11526 ,  G11C11/403 ,  G11C11/4074 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/10 ,  H01L27/115 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/7869

摘要： Provided is a semiconductor memory device including an oxide semiconductor insulated gate FET and having a capability to implement advanced performance without being affected by a variation in threshold voltage. A memory cell MC includes a memory node Nm formed at a connection point of a gate of a first transistor element T1, a source of a second transistor element T2, and one end of a capacitive element Cm, and a control node Nc formed at a connection point of a drain of the first transistor element T1 and a drain of the second transistor element T2. Each memory cell MC arranged in the same column includes the control node Nc connected to a shared first control line CL extending in a column direction, the first transistor element T1 having a source connected to a shared data signal line DL extending in the column direction, the second transistor element T2 having a gate connected to an individual first selection line WL, and the capacitive element Cm having the other end connected to an individual second selection line GL, and a switching element SE having one end connected to the first control line CL, and the other end connected to a voltage supply line VL is provided with respect to each first control line CL.

摘要翻译： 提供了一种半导体存储器件，其包括氧化物半导体绝缘栅极FET，并且具有在不受阈值电压变化的影响的情况下实现高级性能的能力。 存储单元MC包括形成在第一晶体管元件T1的栅极，第二晶体管元件T2的源极和电容元件Cm的一端的连接点处的存储器节点Nm，以及形成在第一晶体管元件 第一晶体管元件T1的漏极和第二晶体管元件T2的漏极的连接点。 布置在同一列中的每个存储单元MC包括连接到沿列方向延伸的共享第一控制线CL的控制节点Nc，第一晶体管元件T1具有连接到沿列方向延伸的共享数据信号线DL的源极， 第二晶体管元件T2具有连接到单独的第一选择线WL的栅极，以及另一端连接到单独的第二选择线GL的电容元件Cm，以及一端连接到第一控制线CL的开关元件SE 并且相对于每个第一控制线CL设置连接到电压供应线VL的另一端。

公开(公告)号：US20150003165A1

公开(公告)日：2015-01-01

申请号：US14371202

申请日：2012-12-28

申请人： Sharp Kabushiki Kaisha

发明人： Yoshimitsu Yamauchi

IPC分类号： H01L27/115 ,  G11C16/10 ,  G11C16/04

CPC分类号： H01L27/11517 ,  G11C11/403 ,  G11C11/405 ,  G11C16/0408 ,  G11C16/10 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1225

摘要： Provided is a semiconductor memory circuit including an oxide semiconductor insulated gate FET enabling advanced performance without being affected by a variation in threshold voltage. A semiconductor memory circuit MC includes a first transistor element T1 composed of an insulated gate FET having a gate electrode connected to a memory node N1, a drain electrode connected to an intermediate node N2, and a source electrode connected to a data I/O terminal DIO; a second transistor element T2 composed of an oxide semiconductor insulated gate FET having a gate electrode connected to a first control terminal CIN1, a drain electrode connected to the intermediate node N2, and a source electrode connected to the memory node N1; a capacitive element C1 having one end connected to a first voltage terminal VIN1 and the other end connected to the memory node N1; and a switching element S1 for controlling a conducting state between a second control terminal CIN2 or a second voltage terminal VIN2 or the first voltage terminal VIN1, and the intermediate node N2, based on a voltage level of at least the second control terminal CIN2.

摘要翻译： 提供了一种半导体存储器电路，其包括具有高性能的氧化物半导体绝缘栅极FET，而不受阈值电压的变化的影响。 半导体存储器电路MC包括：第一晶体管元件T1，其由具有连接到存储节点N1的栅电极，连接到中间节点N2的漏电极和连接到数据I / O端子的源电极的绝缘栅FET构成; DIO; 由具有连接到第一控制端子CIN1的栅电极，连接到中间节点N2的漏电极和连接到存储节点N1的源电极的氧化物半导体绝缘栅FET构成的第二晶体管元件T2; 电容元件C1，其一端连接到第一电压端子VIN1，另一端连接到存储器节点N1; 以及用于基于至少第二控制端子CIN2的电压电平来控制第二控制端子CIN2或第二电压端子VIN2或第一电压端子VIN1与中间节点N2之间的导通状态的开关元件S1。