公开(公告)号：US11935873B2

公开(公告)日：2024-03-19

申请号：US18176058

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Un-Byoung Kang ,  Sunkyoung Seo ,  Jongho Lee ,  Young Kun Jee

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2225/06513

Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.

公开(公告)号：US11621250B2

公开(公告)日：2023-04-04

申请号：US17571796

申请日：2022-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Un-Byoung Kang ,  Sunkyoung Seo ,  Jongho Lee ,  Young Kun Jee

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.

公开(公告)号：US08802495B2

公开(公告)日：2014-08-12

申请号：US13955259

申请日：2013-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang Kim ,  Tae Hong Min ,  Chajea Jo ,  Taeje Cho ,  Young Kun Jee ,  Yun Seok Choi

IPC: H01L21/50 ,  H01L21/56

CPC classification number: H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor package includes preparing a parent substrate including package board parts laterally spaced apart from each other, mounting a first chip including a through-via electrode on each of the package board parts, forming a first mold layer on the parent substrate having the first chips, planarizing the first mold layer to expose back sides of the first chips, etching the exposed back sides of the first chips to expose back sides of the through-via electrodes, forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes, and selectively removing the passivation layer to expose the back sides of the through-via electrodes.

Abstract translation: 制造半导体封装的方法包括：准备包括彼此横向隔开的封装板部分的母基板，在每个封装板部件上安装包括通孔电极的第一芯片，在母基板上形成第一模层 具有第一芯片，平坦化第一模具层以暴露第一芯片的背面，蚀刻第一芯片的暴露的背面以暴露通孔电极的背面，在平坦化的第一模具层上形成钝化层， 第一芯片的蚀刻背面和通孔电极的背面，并且选择性地去除钝化层以暴露通孔电极的背面。