公开(公告)号：US20210358529A1

公开(公告)日：2021-11-18

申请号：US17387036

申请日：2021-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun SHIN ,  Tae-Young OH

IPC: G11C8/06 ,  G11C8/18 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4076 ,  G06F13/16

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US20200278790A1

公开(公告)日：2020-09-03

申请号：US16874916

申请日：2020-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun SHIN ,  Tae-Young OH

IPC: G06F3/06 ,  G11C8/18 ,  G11C8/06 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G06F13/16

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US20170110165A1

公开(公告)日：2017-04-20

申请号：US15298491

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Ran KIM ,  Tae-Young OH

IPC: G11C7/22 ,  G11C8/10 ,  G11C8/18

CPC classification number: G11C8/10 ,  G11C7/1072 ,  G11C7/222 ,  G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: An operating method of a memory device includes entering into a command bus training mode, generating a plurality of internal clock signals by dividing a received clock signal, generating a plurality of internal chip selection signals by latching a received chip selection signal according to the plurality of internal clock signals, generating a second command/address signal by encoding a received first command/address signal based on the plurality of internal chip selection signals, and outputting the second command/address signal.