公开(公告)号：US20240098984A1

公开(公告)日：2024-03-21

申请号：US18368243

申请日：2023-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungeun CHOI ,  Seokho SHIN ,  Joongchan SHIN ,  Kiseok LEE ,  Keunnam KIM ,  Seokhan PARK ,  Eunsuk JANG ,  Jinwoo HAN

IPC: H10B12/00 ,  H01L29/78

CPC classification number: H10B12/482 ,  H01L29/7827 ,  H10B12/315 ,  H10B12/488

Abstract: A semiconductor device may include a substrate, a bitline extending in a first direction on the substrate, and an active pattern on the bitline. The semiconductor device may include a back gate electrode extending beside one side of the active pattern in a second direction perpendicular to the first direction across the bitline, and a wordline extending in the second direction beside the other side of the active pattern. A length of the active pattern in the second direction may be greater than a length of the bitline in the second direction.

公开(公告)号：US20250098154A1

公开(公告)日：2025-03-20

申请号：US18825176

申请日：2024-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun SUNG ,  Seokhan PARK ,  Gyuhwan OH ,  Bowon YOO ,  Jinwoo HAN

IPC: H10B12/00

Abstract: A semiconductor device includes bit lines, which are apart from each other in a first direction and extend in a second direction that crosses the first direction, above a top surface of a substrate, comb-type insulating patterns arranged among the bit lines in the first direction and apart from each other in the second direction, line insulating layers apart from each other in the first direction, extending in the second direction, and covering the bit lines and portions of the comb-type insulating patterns from below, and a conductive line shield layer covering the line insulating layers and the other portions of the comb-type insulating patterns from below.

公开(公告)号：US20250089239A1

公开(公告)日：2025-03-13

申请号：US18804207

申请日：2024-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin PARK ,  Jinwoo HAN ,  Seokhan PARK ,  Gyuhwan OH ,  Bowon YOO

IPC: H10B12/00

Abstract: Provided is a semiconductor memory device including a plurality of word lines extending in a first horizontal direction, a plurality of channel patterns adjacent to a plurality of word line structures, arranged in a row in the first horizontal direction, and extending in a vertical direction, a plurality of bit lines extending in a second horizontal direction different from the first horizontal direction and electrically connected to a plurality of channel patterns, the plurality of word lines adjacent to the plurality of channel patterns, and the plurality of channel patterns on the bit lines, a shield conductive layer arranged below the plurality of bit lines and extending in the vertical direction between the bit lines, and a cover insulating layer arranged between the plurality of bit lines and the shield conductive layer. In a plan view the shield conductive layer comprises a main body unit and a pad unit, the plurality of bit lines overlapping the main body unit in the vertical direction, and a pad unit extending from the main body unit but the plurality of bit lines not overlapping the pad unit in the vertical direction.

公开(公告)号：US20250081441A1

公开(公告)日：2025-03-06

申请号：US18414959

申请日：2024-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bowon YOO ,  Seokhan PARK ,  Gyuhwan OH ,  Jinwoo HAN

IPC: H10B12/00

Abstract: A semiconductor memory device includes a bit line on a peripheral gate structure and extending in a second direction different from a first direction; a shielding structure adjacent to the bit line on the peripheral gate structure and extending in the second direction; a back gate electrode on the bit line and the shielding structure and extending in the first direction; a first word line extending in the first direction and on one side of the back gate electrode in the second direction, and a second word line placed on another side of the back gate electrode, the first and second word lines on the bit line and the shielding structure; and a first activation pattern between the back gate electrode and the first word line and a second activation pattern, the first and second activation patterns on the bit line, wherein the shielding structure includes a low-dielectric material.

公开(公告)号：US20240422961A1

公开(公告)日：2024-12-19

申请号：US18640513

申请日：2024-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongchan SHIN ,  Seokhan PARK ,  Kiseok LEE ,  Moonyoung JEONG ,  Jinwoo HAN

IPC: H10B12/00

Abstract: A semiconductor memory device includes a plurality of word lines extending in a first horizontal direction, a plurality of back gate lines extending in the first horizontal direction and alternately arranged with the plurality of word lines in a second horizontal direction different from the first horizontal direction, a plurality of channel layers extending in a vertical direction between a word line and a back gate line adjacent to each other among the plurality of word lines and the plurality of back gate lines, to correspond to columns in the first horizontal direction, a plurality of bit lines extending in the second horizontal direction on the plurality of word lines, the plurality of back gate lines, and the plurality of channel layers and electrically connected to the plurality of channel layers, and a plurality of memory structures electrically connected to the plurality of channel layers.

公开(公告)号：US20240421223A1

公开(公告)日：2024-12-19

申请号：US18631839

申请日：2024-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongchan SHIN ,  Seokhan PARK ,  Kiseok LEE ,  Moonyoung JEONG ,  Jinwoo HAN

IPC: H01L29/78 ,  H10B12/00

Abstract: A semiconductor device includes a substrate, a bit line extending in a first direction on the substrate, a first active pattern and a second active pattern on the bit line, a back gate electrode extending in a second direction perpendicular to the first direction across the bit line, and a word line extending in the second direction, wherein the first active pattern and the second active pattern have a minor symmetrical shape with respect to the back gate electrode when viewed in a third direction perpendicular to the first direction and the second direction.