公开(公告)号：US20210074720A1

公开(公告)日：2021-03-11

申请号：US16885499

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan Son ,  Sanghoon Jeong ,  Sangjun Hong ,  Seogoo Kang ,  Jeehoon Han

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor device includes a lower structure; a stack structure including gate layers and interlayer insulating layers and having an opening; a vertical structure in the opening; a contact structure on the vertical structure; and a conductive line on the contact structure. The vertical structure includes an insulating core region, a channel semiconductor layer covering side and lower surfaces of the insulating core region, data storage patterns between the channel semiconductor layer and the gate layers and spaced apart from each other, a first dielectric layer, and a second dielectric layer. At least a portion of the first dielectric layer is between the data storage patterns and the gate layers, at least a portion of the second dielectric layer is between the data storage patterns and the channel semiconductor layer, and the insulating core region includes first convex portions having increased widths in regions facing the gate layers.

公开(公告)号：US12268004B2

公开(公告)日：2025-04-01

申请号：US18103070

申请日：2023-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon Ryu ,  Younghwan Son ,  Seogoo Kang ,  Jesuk Moon ,  Junghoon Jun ,  Kohji Kanamori ,  Jeehoon Han

IPC: H10B43/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes; gate layers stacked on a substrate, a channel layer extending through the gate layers, a string select gate layer disposed on the channel layer and a string select channel layer extending through the string select gate layer to contact the channel layer. The string select channel layer includes a first portion below the string select gate layer including a first protruding region, a second portion extending through the string select gate layer, and a third portion above the string select gate layer including a second protruding region.

公开(公告)号：US20250071994A1

公开(公告)日：2025-02-27

申请号：US18767830

申请日：2024-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Seogoo Kang ,  Kyungdong Kim ,  Seunghyun Lee ,  Junghoon Jun ,  Jeehoon Han ,  Taeyoon Hong

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a gate electrode structure, a memory channel structure, and a first contact plug. The gate electrode structure is disposed on a substrate, and includes gate electrodes spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate. Each of the gate electrode extends in a second direction substantially parallel to the upper surface of the substrate. The memory channel structure extends through the gate electrode structure on the substrate. The first contact plug extends in the first direction on the substrate through and contacting a corresponding one of the gate electrodes, and a portion of a sidewall of the first contact plug at substantially the same level as the corresponding one of the gate electrodes is not surrounded by the corresponding one of the gate electrodes.

公开(公告)号：US11792994B2

公开(公告)日：2023-10-17

申请号：US17659990

申请日：2022-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Seogoo Kang ,  Jongseon Ahn ,  Jeehoon Han

IPC: H10B43/35 ,  H01L29/49 ,  H01L21/28 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/35 ,  H01L21/28052 ,  H01L29/4933 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide.

公开(公告)号：US11637117B2

公开(公告)日：2023-04-25

申请号：US17032277

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon Ryu ,  Kwanyong Kim ,  Seogoo Kang ,  Sunil Shim ,  Wonseok Cho ,  Jeehon Han

IPC: H01L27/1157 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11565

Abstract: A semiconductor device includes; a memory stack disposed on a substrate and including a lower gate electrode, an upper gate stack including a string selection line, a vertically extending memory gate contact disposed on the lower gate electrode, and a vertically extending selection line stud disposed on the string selection line. The string selection line includes a material different from that of the lower gate electrode, and the selection line stud includes a material different from that of the memory gate contact.

公开(公告)号：US11444098B2

公开(公告)日：2022-09-13

申请号：US16850244

申请日：2020-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghwan Son ,  Seungwon Lee ,  Seogoo Kang ,  Juyoung Lim ,  Jeehoon Han

IPC: H01L27/11582 ,  H01L29/51 ,  H01L29/49 ,  H01L23/528 ,  H01L23/522 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/28

Abstract: A vertical non-volatile memory device includes a channel on a substrate and extending in a first direction perpendicular to an upper surface of the substrate, a first charge storage structure on an outer sidewall of the channel, a second charge storage structure on an inner sidewall of the channel, first gate electrodes spaced apart from each other in the first direction on the substrate, each which surrounds the first charge storage structure, and a second gate electrode on an inner sidewall of the second charge storage structure.

公开(公告)号：US11411078B2

公开(公告)日：2022-08-09

申请号：US16701427

申请日：2019-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon Ryu ,  Kiyoon Kang ,  Seogoo Kang ,  Shinhwan Kang ,  Jesuk Moon ,  Byunggon Park ,  Jaeryong Sim ,  Jinsoo Lim ,  Jisung Cheon ,  Jeehoon Han

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L29/06 ,  H01L23/31 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.