公开(公告)号：US11335695B2

公开(公告)日：2022-05-17

申请号：US16710402

申请日：2019-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisung Cheon ,  Byunggon Park ,  Joowon Park ,  Sangjun Hong ,  Jinsoo Lim

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/28 ,  H01L23/535

Abstract: An integrated circuit device including a substrate having a cell and interconnection region; and a first stacked structure and a second stacked structure on the first stacked structure, each of the first and second stacked structures including insulating layers and word line structures that are alternately stacked one by one on the substrate in the cell region and the interconnection region, wherein, in the interconnection region the first stacked structure includes a first dummy channel hole penetrating through the first stacked structure, the second stacked structure includes a second dummy channel hole communicatively connected to the first dummy channel hole, the second dummy channel hole penetrating through the second stacked structure, respectively, and a first dummy upper width of an uppermost end of the first dummy channel hole is greater than a second dummy upper width of an uppermost end of the second dummy channel hole.

公开(公告)号：US20210193678A1

公开(公告)日：2021-06-24

申请号：US16926045

申请日：2020-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiye Noh ,  Jinsoo Lim ,  Daehyun Jang ,  Jisung Cheon ,  Sangjun Hong

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/48 ,  H01L23/528

Abstract: A semiconductor device includes a peripheral circuit structure disposed on a substrate; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack, the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.