公开(公告)号：US11069597B2

公开(公告)日：2021-07-20

申请号：US16366267

申请日：2019-03-27

申请人： Samsung Electronics Co., Ltd.

发明人： Dae-suk Lee ,  Hak-seung Lee ,  Dong-chan Lim ,  Tae-seong Kim ,  Kwang-jin Moon

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532 ,  H01L25/18

摘要： Semiconductor chips and methods of manufacturing the same are provided. The semiconductor chip includes a substrate, an interlayer insulation layer including a bottom interlayer insulation layer on an upper surface of the substrate and a top interlayer insulation layer on the bottom interlayer insulation layer, an etch stop layer between the bottom interlayer insulation layer and the top interlayer insulation layer, a landing pad on the interlayer insulation layer, and a through via connected to the landing pad through the substrate, the interlayer insulation layer, and the etch stop layer. The etch stop layer is isolated from direct contact with the landing pad.

公开(公告)号：US11018101B2

公开(公告)日：2021-05-25

申请号：US16398888

申请日：2019-04-30

申请人： Samsung Electronics Co., Ltd.

发明人： Ju-il Choi ,  Kwang-jin Moon ,  Ju-bin Seo ,  Dong-chan Lim ,  Atsushi Fujisaki ,  Ho-jin Lee

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18

摘要： A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.

公开(公告)号：US10325869B2

公开(公告)日：2019-06-18

申请号：US15870044

申请日：2018-01-12

申请人： Samsung Electronics Co., Ltd.

发明人： Ju-il Choi ,  Kwang-jin Moon ,  Ju-bin Seo ,  Dong-chan Lim ,  Atsushi Fujisaki ,  Ho-jin Lee

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

摘要： A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer

公开(公告)号：US20180370210A1

公开(公告)日：2018-12-27

申请号：US15845458

申请日：2017-12-18

申请人： Samsung Electronics Co., Ltd.

发明人： Tae-yeong Kim ,  Pil-kyu Kang ,  Seok-ho Kim ,  Kwang-jin Moon ,  Na-ein Lee ,  Ho-jin Lee

IPC分类号： B32B37/10 ,  H01L21/67 ,  H01L21/687 ,  H01L21/68 ,  H01L23/00

摘要： Provided are a wafer bonding apparatus for accurately detecting a bonding state of wafers in a wafer bonding process and/or in a wafer bonding system including the wafer bonding apparatus. The wafer bonding apparatus includes a first supporting plate including a first surface and vacuum grooves for vacuum-absorption of a first wafer disposed on the first surface, a second supporting plate including a second surface facing the first surface. A second wafer is on the second surface. The wafer bonding apparatus and/or the wafer bonding system include a bonding initiator at a center portion of the first supporting plate, and an area sensor on the first supporting plate and configured to detect a propagation state of bonding between the first wafer and the second wafer.