公开(公告)号：US11264454B2

公开(公告)日：2022-03-01

申请号：US16719175

申请日：2019-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-sic Yoon ,  Ho-in Lee ,  Ki-seok Lee ,  Je-min Park

IPC: H01L27/11573 ,  H01L29/06 ,  H01L21/762 ,  H01L27/108 ,  G11C11/408

Abstract: An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.

公开(公告)号：US10580876B2

公开(公告)日：2020-03-03

申请号：US15914611

申请日：2018-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-hyeok Ahn ,  Eun-jung Kim ,  Hui-jung Kim ,  Ki-seok Lee ,  Bong-soo Kim ,  Myeong-dong Lee ,  Sung-hee Han ,  Yoo-sang Hwang

IPC: H01L29/423 ,  H01L21/74 ,  H01L21/762 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

公开(公告)号：US10373961B2

公开(公告)日：2019-08-06

申请号：US15884504

申请日：2018-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-sic Yoon ,  Ki-seok Lee ,  Jung-hyun Kim ,  Je-min Park

IPC: H01L29/00 ,  H01L27/108 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor device includes first wiring line patterns on a support layer, second wiring line patterns on the first wiring line patterns, and a multiple insulation pattern. The first wiring line patterns extend in a first direction and are spaced apart from each other in a second direction. The support layer includes first contact hole patterns between the first wiring line patterns that are spaced apart from each other in the first and second directions. The second wiring line patterns extend in the second direction perpendicular and are spaced apart from each other in the first direction. The multiple insulation pattern is on an upper surface of the support layer where the first contact hole patterns are not formed, arranged in a third direction perpendicular to the first direction and the second direction, and between the first wiring line patterns and the second wiring line patterns.