公开(公告)号：US11189633B2

公开(公告)日：2021-11-30

申请号：US16700801

申请日：2019-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo Lim ,  Kyungwook Park ,  Keun Lee ,  Hauk Han

IPC: H01L27/11582 ,  H01L29/423 ,  H01L21/67 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/285 ,  H01L21/3213 ,  C23C16/56 ,  C23C16/455 ,  C23C16/06 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.

公开(公告)号：US10734493B2

公开(公告)日：2020-08-04

申请号：US16029993

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Je-hyeon Park ,  Do-hyung Kim ,  Tae-yong Kim ,  Keun Lee ,  Jeong-gil Lee ,  Hyun-seok Lim

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/786

Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.