SEMICONDUCTOR DEVICE INCLUDING ELECTROSTATIC DISCHARGE (ESD) CIRCUIT

    公开(公告)号:US20250169192A1

    公开(公告)日:2025-05-22

    申请号:US18674705

    申请日:2024-05-24

    Abstract: A semiconductor device includes a first pad configured to receive and transmit a signal; a second pad to which a predetermined reference voltage is input; and an electrostatic protection circuit includes an emitter region electrically connected to the second pad and doped with a first conductivity-type impurity, a base region having a shape surrounding the emitter region in the first direction and the second direction and doped with a second conductivity-type impurity, different from the first conductivity-type impurity, a collector region connected to the first pad and having a shape surrounding the emitter region in the first direction and the second direction, and an impurity region disposed between the collector region and the base region and separated from the collector region and the base region by an element isolation film.

    Image output method and electronic device supporting same

    公开(公告)号:US12254905B2

    公开(公告)日:2025-03-18

    申请号:US18103080

    申请日:2023-01-30

    Abstract: An electronic device includes: a display; and a processor configured to: play a video on the display by using a first application, obtain playback information associated with playing the video by using the first application, activate a second application while the video is played by using the first application, determine a frame of the video corresponding to a time point at which the second application is activated, and seek the frame to play the video by using the second application, based on the second application being able to seek the frame within a reference time.

    Electronic device for processing video and method for operating the same

    公开(公告)号:US12238452B2

    公开(公告)日:2025-02-25

    申请号:US18103422

    申请日:2023-01-30

    Abstract: Disclosed is an electronic device including a display module and a processor. The processor is configured to obtain a first video frame and a bypass control value for the first video frame and determine whether to perform frame rate conversion (FRC) processing using the first video frame based on the bypass control value. Based on a determination that the bypass control value is set to a first value indicating bypass of the FRC processing, the processor is configured to display the first video frame. Based on a determination that the bypass control value is set to a second value indicating the FRC processing, the processor is configured to generate an interpolation frame using the first video frame and a second video frame after the first video frame, and display the first video frame, the interpolation frame, and the second video frame.

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