公开(公告)号：US20190079177A1

公开(公告)日：2019-03-14

申请号：US15920990

申请日：2018-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaesup LEE ,  Sungdo CHOI ,  Byung Kwan KIM

IPC: G01S13/90 ,  G01S13/93

Abstract: A radar image processing method includes acquiring captured images from radars synchronized to perform beamforming on a same point at a same time, synthesizing the captured images based on at least one overlapping area of the captured images, and generating a high-resolution image based on the synthesized images.

公开(公告)号：US20190064340A1

公开(公告)日：2019-02-28

申请号：US15877967

申请日：2018-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghan KIM ,  Jaesup LEE

IPC: G01S13/58

CPC classification number: G01S13/58 ,  G01S7/023 ,  G01S7/354 ,  G01S13/325 ,  G01S13/93 ,  G01S13/931

Abstract: A method performed by an apparatus included in a vehicle to detect an object using a radar includes: propagating, in a normal mode period of an operating period for detecting objects, a normal mode transmission signal generated based on a default code sequence including at least two codes; receiving a normal mode reception signal in the normal mode period; detecting, in the normal mode period, an object based on the default code sequence and the normal mode reception signal; receiving a listening mode reception signal in a listening mode period of the operating period; acquiring a correlation between the listening mode reception signal and the default code sequence; and changing the default code sequence based on the correlation.

公开(公告)号：US20160241229A1

公开(公告)日：2016-08-18

申请号：US14863935

申请日：2015-09-24

Applicant: Samsung Electronics Co., Ltd. ,  Postech Academy-Industry Foundation

Inventor： Jaesup LEE ,  Tae-Young CHUNG ,  Bum-Man KIM ,  Dae-Chul JEONG

IPC: H03K17/284

CPC classification number: H03K17/292 ,  H03K5/131 ,  H03K17/284 ,  H03K2005/00019 ,  H03K2005/00195

Abstract: A leakage current-based delay circuit is provided, wherein the delay circuit may include a first transistor circuit and a second transistor circuit, each transistor circuit may include a p-type transistor, an n-type transistor, an n-node between a drain node of the p-type transistor and a gate node of the n-type transistor, and a p-node between a gate node of the p-type transistor and a drain node of the n-type transistor. The p-node of the second transistor circuit may be charged based on a power source voltage through the first transistor circuit during a first time interval of an input signal, and the n-node of the second transistor circuit may be discharged based on a ground voltage through the first transistor circuit during the first time interval.

Abstract translation: 提供了一种基于泄漏电流的延迟电路，其中延迟电路可以包括第一晶体管电路和第二晶体管电路，每个晶体管电路可以包括p型晶体管，n型晶体管，漏极之间的n结 p型晶体管的节点和n型晶体管的栅极节点以及p型晶体管的栅极节点和n型晶体管的漏极节点之间的p节点。 可以在输入信号的第一时间间隔期间，基于通过第一晶体管电路的电源电压对第二晶体管电路的p节点进行充电，并且第二晶体管电路的n个节点可以基于地 在第一时间间隔期间通过第一晶体管电路的电压。