公开(公告)号：US11888476B2

公开(公告)日：2024-01-30

申请号：US17591093

申请日：2022-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daehyun Kwon ,  Hyejung Kwon ,  Hyeran Kim ,  Chisung Oh

IPC: H03K19/017 ,  H03K19/00 ,  H03K19/17736 ,  H03K19/17772

CPC classification number: H03K19/01742 ,  H03K19/0005 ,  H03K19/1774 ,  H03K19/17772

Abstract: An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

公开(公告)号：US20240029808A1

公开(公告)日：2024-01-25

申请号：US18174186

申请日：2023-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yujung Song ,  Sungrae Kim ,  Gilyoung Kang ,  Hyeran Kim ,  Chisung Oh

IPC: G11C29/42 ,  G11C29/46 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/46 ,  G11C29/1201

Abstract: A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine and a control logic circuit. The on-die ECC engine includes a first latch and a second latch. The control logic circuit sets the semiconductor memory device to a test mode in response to a first mode register set command. The on-die ECC engine, in the test mode, cuts off a connection with the memory cell array, receives a test data, stores the test data in the first latch, performs an ECC decoding on the test data stored in the first latch and a test parity data, stored in the second latch in response to a read command and provides an external device with a severity signal indicating whether the test data and the test parity data includes at least one error bit and the at least one error bit is correctable.

公开(公告)号：US20230377669A1

公开(公告)日：2023-11-23

申请号：US18134776

申请日：2023-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonyoung Choi ,  Gilyoung Kang ,  Sungrae Kim ,  Hyeran Kim ,  Jeongseok Park ,  Changkyu Seol

IPC: G11C29/36 ,  G11C29/14 ,  G11C29/38

CPC classification number: G11C29/36 ,  G11C29/14 ,  G11C29/38

Abstract: A memory device, an operating method of the memory device, and a test system including the memory device. The memory device may include a decoder group configured to receive a plurality of codewords including a plurality of symbols from outside of the memory device and to decode the plurality of codewords into data patterns, a memory cell array configured to store the data patterns received from the decoder group and including a plurality of memory cells, and an encoder configured to encode the data patterns into the plurality of codewords including the plurality of symbols. The plurality of codewords may include illegal codewords and normal codewords, and the decoder group may be further configured to convert the illegal codewords among the plurality of codewords into fixed patterns, and the encoder may be configured to output the plurality of codewords to the outside of the memory device.