公开(公告)号：US11531871B2

公开(公告)日：2022-12-20

申请号：US16854942

申请日：2020-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehun Jang ,  Hongrak Son ,  Changkyu Seol ,  Geunyeong Yu ,  Chanho Yoon ,  Pilsang Yoon

IPC: G06N3/04 ,  H01L25/18 ,  G06N3/063 ,  H01L25/065

Abstract: A stacked neuromorphic device includes a logic die including a control circuit and configured to communicate with a host, and core dies stacked on the logic die and connected to the logic die via through silicon vias (TSVs) extending through the core dies. The core dies include a neuromorphic core die including a synapse array connected to row lines and column lines. The synapse array includes synapses configured to store weights and perform a calculation based on the weights and input data. The weights are included in layers of a neural network system. And the control circuit provides the weights to the neuromorphic core die through the TSVs and controls data transmission by the neuromorphic core die.

公开(公告)号：US11119692B2

公开(公告)日：2021-09-14

申请号：US16510029

申请日：2019-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonwu Kim ,  Daekyoung Kim ,  Seok-Won Ahn ,  Chanho Yoon

IPC: G06F3/06 ,  G11C16/32 ,  G11C16/08 ,  G11C16/04

Abstract: A method of operating a controller which controls a nonvolatile memory device includes enabling a command latch enable signal, an address latch enable signal, and a write enable signal and transmitting multiple data signals including a command and an address to the nonvolatile memory device in synchronization with the enabled write enable signal. A number of DQ lines through which the plurality of data signals are transmitted is greater than a number of bits of each of the data signals. The method also include disabling the command latch enable signal after the command is transmitted, and disabling the address latch enable signal and the write enable signal after the address is transmitted.

公开(公告)号：US20200150893A1

公开(公告)日：2020-05-14

申请号：US16510029

申请日：2019-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonwu Kim ,  Daekyoung Kim ,  Seok-Won Ahn ,  Chanho Yoon

IPC: G06F3/06 ,  G11C16/32

Abstract: A method of operating a controller which controls a nonvolatile memory device includes enabling a command latch enable signal, an address latch enable signal, and a write enable signal and transmitting multiple data signals including a command and an address to the nonvolatile memory device in synchronization with the enabled write enable signal. A number of DQ lines through which the plurality of data signals are transmitted is greater than a number of bits of each of the data signals. The method also include disabling the command latch enable signal after the command is transmitted, and disabling the address latch enable signal and the write enable signal after the address is transmitted.