公开(公告)号：US09455284B2

公开(公告)日：2016-09-27

申请号：US14602427

申请日：2015-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung-Jun Park ,  Seung-Hun Shin ,  Chang-Rok Moon ,  Tae-Seok Oh ,  June-Taeg Lee

IPC: H01L27/146

CPC classification number: H01L27/14605 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/14612 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14687

Abstract: A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench.

Abstract translation: 堆叠型图像传感器可以包括：第一芯片，其包括穿过第一衬底的通孔隔离沟槽，在通孔隔离沟槽中包括绝缘材料的通孔隔离层，第一衬底上的第一导电层和第一绝缘层; 第二芯片，包括在第二基板上的第二导电层，以及与第一绝缘层接触的第二绝缘层; 穿过所述第一衬底以相对于所述沟槽暴露所述第二导电层的第一通孔沟槽; 以及形成在所述第一通孔沟槽中的第一通孔，并且包括通过所述通孔隔离层与所述第一基板绝缘的第三导电层，所述第三导电层将所述第一导电层电连接到所述第二导电层。 第三导电层可以形成在通孔隔离沟槽中。

公开(公告)号：US20150221695A1

公开(公告)日：2015-08-06

申请号：US14561854

申请日：2014-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung-Jun Park ,  Chang-Rok Moon ,  Seung-Hun Shin ,  Seong-Ho Oh ,  Tae-Seok Oh ,  June-Taeg Lee

IPC: H01L27/146 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L27/14636 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/1469 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

Abstract translation: 半导体器件包括下部器件和设置在下部器件上的上部器件。 下部器件包括下部衬底，设置在下部衬底上的下部插头焊盘以及下部插头焊盘上的下部层间电介质层。 上部器件包括上部衬底，上部衬底的下部中的蚀刻延迟结构，设置在上部衬底的底部表面上的上部焊盘，位于上部焊盘上的上层间绝缘层，以及通孔 插头被配置为穿透上基板并接触上插头垫和下插头垫。 通孔插头包括与上插头焊盘和第一蚀刻延迟结构接触的第一部分，以及与下插头焊盘接触的第二部分。