Abstract:
A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.
Abstract:
A gate driver, including multiple stages of gate driving circuits, wherein each stage of the gate driving circuits includes an input part configured to generate a Q node signal in response to a carry signal of one of previous stages and a clock signal, the Q node signal being applied to Q node, an output part configured to output a gate output signal to a gate output terminal in response to the Q node signal, and a charge sharing part connected to the gate output terminal of a present stage and a gate output terminal of one of next stages, the charge sharing part configured to operate charge-sharing between the gate output signal of the present stage and a gate output signal of one of the next stages in response to a select signal.
Abstract:
A liquid crystal display panel with enhanced image quality is disclosed. The liquid crystal display panel has a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors connected to gate line and data line, a plurality of pixel electrodes, and floating electrode(s). The floating electrode extends along the data line to prevent light leakage and vertical crosstalk. Throughout the whole liquid crystal display panel, the floating electrode is electrically interconnected to lessen vertical crosstalk.
Abstract:
A display device includes pixels, gate lines, and data lines on a substrate. The pixels include sub-pixels, and each sub-pixel includes a respective one of a plurality of first electrodes connected to one of the gate lines and one of the data lines. The first electrode of the sub-pixel at an n-th row and the first electrode of the sub-pixel at an (n+2)-th row in a same column are connected to different ones of the data lines. The sub-pixels in the n-th and (n+2)-th rows in the same column emit the same color of light.
Abstract:
A liquid crystal display panel with enhanced image quality is disclosed. The liquid crystal display panel has a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors connected to gate line and data line, a plurality of pixel electrodes, and floating electrode(s). The floating electrode extends along the data line to prevent light leakage and vertical crosstalk. Throughout the whole liquid crystal display panel, the floating electrode is electrically interconnected to lessen vertical crosstalk.
Abstract:
A liquid crystal display panel with enhanced image quality is disclosed. The liquid crystal display panel has a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors connected to gate line and data line, a plurality of pixel electrodes, and floating electrode(s). The floating electrode extends along the data line to prevent light leakage and vertical crosstalk. Throughout the whole liquid crystal display panel, the floating electrode is electrically interconnected to lessen vertical crosstalk.
Abstract:
A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.
Abstract:
A gate driving circuit and a display apparatus having the gate driving circuit, in which the gate driving circuit includes a voltage adjusting part using a low clock signal to increase the reliability of the gate driving circuit, thereby extending the lifetime of the gate driving circuit.
Abstract:
A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, a first line connecting part disposed in the peripheral region that includes the first conductive pattern, a second conductive pattern that overlaps the first conductive pattern and formed, an organic layer that partially exposes the second conductive pattern, and a third conductive pattern electrically connected to the second conductive pattern that contacts the partially exposed second conductive pattern, and a fourth conductive pattern that electrically connects the first conductive pattern of the pad part and the third conductive pattern of the first line connecting part.
Abstract:
A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, a first line connecting part disposed in the peripheral region that includes the first conductive pattern, a second conductive pattern that overlaps the first conductive pattern and formed, an organic layer that partially exposes the second conductive pattern, and a third conductive pattern electrically connected to the second conductive pattern that contacts the partially exposed second conductive pattern, and a fourth conductive pattern that electrically connects the first conductive pattern of the pad part and the third conductive pattern of the first line connecting part.