公开(公告)号：US20240057411A1

公开(公告)日：2024-02-15

申请号：US18143402

申请日：2023-05-04

Applicant: Samsung Display Co., Ltd.

Inventor： Jin Sung AN ,  Sung Ho KIM ,  Yong Jae KIM ,  Yun Hwan PARK ,  Yoon Jee SHIN ,  Sug Woo JUNG ,  Hyun Wook CHOI

IPC: H10K59/131 ,  H10K59/88 ,  G09G3/3233

CPC classification number: H10K59/131 ,  H10K59/88 ,  G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0861 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2310/02

Abstract: A display device comprises a substrate; a circuit array layer comprising pixel drivers, data lines, first dummy lines, and second dummy lines; and a light emitting array layer. The display area comprises middle, first side, and second side regions. The data lines comprise first, second, and third data lines disposed in the middle, first side, and second side regions, respectively. The first dummy lines comprise a first data detour line disposed in the first side region and adjacent to a part of the second data line, and auxiliary lines. The second dummy lines comprise a second data detour line configured to connect the first data detour line to the third data line, and additional lines. The auxiliary lines comprise a bias auxiliary line to which a bias power is applied; and a second power auxiliary line to which a second power is applied.

公开(公告)号：US20230380256A1

公开(公告)日：2023-11-23

申请号：US18363944

申请日：2023-08-02

Applicant: Samsung Display Co., LTD.

Inventor： Wang Woo LEE ,  Sung Ho KIM ,  Hyeon Sik KIM ,  Joon Hyoung PARK ,  Seok Je SEONG ,  Jin Sung AN ,  Jin Seok OH ,  Min Woo WOO ,  Ji Seon LEE ,  Pil Suk LEE ,  Yun Sik JOO

IPC: H10K77/10 ,  H10K59/131 ,  H10K59/121 ,  H10K71/00 ,  H10K71/80

CPC classification number: H10K77/111 ,  H10K59/131 ,  H10K59/1213 ,  H10K71/00 ,  H10K71/80 ,  H01L27/1218

Abstract: A display device includes a supporting substrate including a polymeric material, base substrate disposed on an upper surface of the supporting substrate, a pixel array disposed in a display area of the base substrate, a transfer wiring disposed in a bending area of the base substrate and electrically connected to the pixel array, and an organic filling portion disposed under the transfer wiring in the bending area. The base substrate includes an organic film including a polymeric material, and an inorganic barrier film overlapping the organic film and extending outwardly from an edge of the organic film. The organic filling portion contacts the organic film of the base substrate.

公开(公告)号：US20220246710A1

公开(公告)日：2022-08-04

申请号：US17408534

申请日：2021-08-23

Applicant: Samsung Display Co., Ltd.

Inventor： Min Woo WOO ,  Sung Ho KIM ,  Seok Je SEONG ,  Jin Sung AN ,  Wang Woo LEE ,  Ji Seon LEE

IPC: H01L27/32

Abstract: An embodiment provides a light emitting display device, including a display panel including a display area, wherein the display area of the display panel includes: a transparent display area; an intermediate display area that is disposed at one side or both sides of the transparent display area along a first direction and includes a pixel circuit part for a transparent display area; and a normal display area, and wherein the transparent display area includes: a first anode; and a transmission transistor that transmits an emission current outputted from the pixel circuit part for the transparent display area to the first anode.

公开(公告)号：US20210097937A1

公开(公告)日：2021-04-01

申请号：US17118903

申请日：2020-12-11

Applicant: Samsung Display Co., Ltd.

Inventor： Seong Min WANG ,  Yong Ho YANG ,  Sung Ho KIM ,  Young-In HWANG

IPC: G09G3/3258 ,  H01L27/32 ,  H01L51/00

Abstract: An organic light emitting diode display includes a first transistor disposed on a substrate and including a gate electrode, an input electrode, and an output electrode, a second transistor electrically connected to a scan line, a data line, and the input electrode of the first transistor, a third transistor including a gate electrode, a first electrode electrically connected to the output electrode of the first transistor, and a second electrode electrically connected to the gate electrode of the first transistor, and an overlapping layer that overlaps the gate electrode of the third transistor in a plan view. The overlapping layer is disposed between the substrate and a semiconductor layer of the third transistor.

公开(公告)号：US20170322435A1

公开(公告)日：2017-11-09

申请号：US15584975

申请日：2017-05-02

Applicant: Samsung Display Co. Ltd.

Inventor： Kang Bin YI ,  Dong Rak KO ,  Sung Ho KIM ,  Eun Ji SEO ,  Sung Hun SON ,  Hee Kyun SHIN ,  Seok Lyul YOON ,  Jeong Seok LEE ,  Sung Wook JUNG ,  Hwan Kyeong JEONG

IPC: G02F1/1333 ,  B24B7/24

Abstract: A display device includes first and second substrates each including a short side and a long side, ground parts located on at least one of the short and long sides of each of the first and second substrates and including at least one first ground surfaces, which are perpendicular to opposing surfaces of the first and second substrates, and at least one second ground surfaces, which are provided at at least one edge of the second substrate to define an obtuse angle with reference to the first ground surfaces, and unevenness disposed on the first ground surfaces along a first direction, where the unevenness defines an acute angle with reference to a normal line to the opposing surfaces.

公开(公告)号：US20230368734A1

公开(公告)日：2023-11-16

申请号：US18226355

申请日：2023-07-26

Applicant: Samsung Display Co., Ltd.

Inventor： Young-In HWANG ,  Sung Ho KIM ,  Eung Taek KIM ,  Yong Ho YANG ,  Seong Min WANG ,  Jung-Mi CHOI

IPC: G09G3/3233 ,  G09G3/3291 ,  G09G3/3266 ,  G09G3/3258 ,  H10K59/131

CPC classification number: G09G3/3233 ,  G09G3/3291 ,  G09G3/3266 ,  G09G3/3258 ,  H10K59/131 ,  G09G2320/0214 ,  G09G2300/0809 ,  G09G2300/0426

Abstract: A pixel includes: an organic light emitting diode; a first transistor including a gate that is connected to a first node, wherein the first transistor is connected between a second node and a third node; a second transistor including a gate that is connected to a corresponding scan line, wherein the second transistor is connected between a data line and the second node; a storage capacitor connected between the first node and a first voltage; a third transistor including a gate that is connected to the corresponding scan line, the third transistor is connected between the first node and the third node; and a fourth transistor connected between a first end of the first transistor and a second voltage.

公开(公告)号：US20230171994A1

公开(公告)日：2023-06-01

申请号：US17879051

申请日：2022-08-02

Applicant: Samsung Display Co., Ltd.

Inventor： Wang Woo LEE ,  Sung Ho KIM ,  Seok Je SEONG ,  Jin Sung AN ,  Min Woo WOO ,  Seung Hyun LEE ,  Ji Seon LEE ,  Yoon-Jong CHO

IPC: H01L51/52 ,  H01L27/32

CPC classification number: H01L51/5284 ,  H01L27/3234 ,  H01L27/3276

Abstract: The present disclosure relates to a light emitting display device that includes a transparent display area including a light transmission area and a normal display area, wherein the transparent display area includes: an anode including an opening; a first light blocking part filling the opening; and a second light blocking part positioned along an exterior side of the anode. A height of a highest part of the first light blocking part is different than a height of a highest part of the second light blocking part.

公开(公告)号：US20220392405A1

公开(公告)日：2022-12-08

申请号：US17891877

申请日：2022-08-19

Applicant: Samsung Display Co., Ltd.

Inventor： Young-In HWANG ,  Sung Ho KIM ,  Eung Taek KIM ,  Yong Ho YANG ,  Seong Min WANG ,  Jung-Mi CHOI

IPC: G09G3/3233 ,  G09G3/3291 ,  G09G3/3266 ,  H01L27/32 ,  G09G3/3258

Abstract: A pixel includes: an organic light emitting diode; a first transistor including a gate that is connected to a first node, wherein the first transistor is connected between a second node and a third node; a second transistor including a gate that is connected to a corresponding scan line, wherein the second transistor is connected between a data line and the second node; a storage capacitor connected between the first node and a first voltage; a third transistor including a gate that is connected to the corresponding scan line, the third transistor is connected between the first node and the third node; and a fourth transistor connected between a first end of the first transistor and a second voltage.

公开(公告)号：US20210208432A1

公开(公告)日：2021-07-08

申请号：US17208372

申请日：2021-03-22

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Bin YI ,  Dong Rak KO ,  Sung Ho KIM ,  Eun Ji SEO ,  Sung Hun SON ,  Hee Kyun SHIN ,  Seok Lyul YOON ,  Jeong Seok LEE ,  Sung Wook JUNG ,  Hwan Kyeong JEONG

IPC: G02F1/1333 ,  B24B7/24

Abstract: A display device includes first and second substrates each including a short side and a long side, ground parts located on at least one of the short and long sides of each of the first and second substrates and including at least one first ground surfaces, which are perpendicular to opposing surfaces of the first and second substrates, and at least one second ground surfaces, which are provided at at least one edge of the second substrate to define an obtuse angle with reference to the first ground surfaces, and unevenness disposed on the first ground surfaces along a first direction, where the unevenness defines an acute angle with reference to a normal line to the opposing surfaces.

公开(公告)号：US20200373335A1

公开(公告)日：2020-11-26

申请号：US16991245

申请日：2020-08-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sung Ho KIM ,  Dong Won KIM ,  Jong Moo HUH

IPC: H01L27/12 ,  H01L27/32 ,  H01L29/786

Abstract: A thin film transistor array panel includes a substrate and a thin film transistor disposed on a surface of the substrate. The thin film transistor includes a semiconductor, a source electrode, and a drain electrode that are disposed on a same layer as one another. The semiconductor is between the source electrode and the drain electrode. The thin film transistor array panel further includes a buffer layer disposed between the semiconductor and the substrate and including an inorganic insulating material. The first edge of the buffer layer is substantially parallel to an adjacent edge of the semiconductor, a second edge of the buffer layer is substantially parallel to an adjacent edge of the source electrode, and a third edge of the buffer layer is substantially parallel to an adjacent edge of the drain electrode.