公开(公告)号：US20210201792A1

公开(公告)日：2021-07-01

申请号：US16940788

申请日：2020-07-28

Applicant: Samsung Display Co., Ltd.

Inventor： Dae Sik LEE ,  Si Duk SUNG ,  Sang Hyun LEE

IPC: G09G3/3258 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3233

Abstract: A power management driver and a display device having the power management driver are provided, including a first power supply configured to supply a first voltage to a first driving power terminal of a pixel through a power line during a sensing period, and supply a second voltage to the first driving power terminal of the pixel through the power line during a display period; a controller configured to control timing at which the first voltage is output and timing at which the second voltage is output during a transition period between the display period and the sensing period in response to a sensing control signal; and a fault detector configured to detect a fault in the power line based on a current flowing through an output terminal during the sensing period.

公开(公告)号：US20210166616A1

公开(公告)日：2021-06-03

申请号：US16898439

申请日：2020-06-11

Applicant: Samsung Display Co., Ltd.

Inventor： Sang Hyun LEE ,  Si Duk SUNG ,  Dae-Sik LEE

IPC: G09G3/32

Abstract: The current disclosure relates to a display device including a display panel including a plurality of pixels, and a plurality of gate lines and a plurality of data lines connected to the plurality of pixels, a gate driver applying a gate signal to the plurality of gate lines, a data driver applying a data signal to the plurality of data lines, and a voltage provider configured to generate a gate-on voltage that is gradually changed in one frame and a kickback voltage that is gradually changed in one frame to transmit the gate-on voltage and the kickback voltage to the gate driver.

公开(公告)号：US20210074194A1

公开(公告)日：2021-03-11

申请号：US16861926

申请日：2020-04-29

Applicant: Samsung Display Co., Ltd.

Inventor： Si Duk SUNG ,  Sang Hyun LEE ,  Bo Yeon KIM

IPC: G09G3/20

Abstract: A display device includes a display panel, a power supply, a signal controller configured to generate first and second clock signals having a period, a clock signal generator configured to generate a gate clock signal that is raised to a high level voltage in synchronization with the first clock signal, and that falls to a low level voltage in synchronization with the second clock signal, generate a panel separation signal by comparing a voltage of the gate clock signal with a first reference voltage during a falling period during which the gate clock signal falls, and transfer the panel separation signal to the power supply or the signal controller, and a gate driver configured to sequentially apply a gate signal by using the gate clock signal, wherein the power supply or the signal controller is configured to stop outputting depending on the panel separation signal.