公开(公告)号：US12100355B2

公开(公告)日：2024-09-24

申请号：US18217924

申请日：2023-07-03

Applicant: Samsung Display Co., Ltd.

Inventor： Nackhyeon Keum ,  Kimyeong Eom ,  Kwangsae Lee

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2330/021

Abstract: Provided is a gate driver including a plurality of stages, wherein each stage includes an output unit including a pull-up transistor and a pull-down transistor, and a second node controller configured to control a voltage of a second control node to which a gate of the pull-up transistor is connected, wherein the second node controller includes a first control transistor connected between the first clock terminal and the second control node and including a gate connected to the first control node, and a second control transistor including a gate connected to the gate of the first control transistor and configured to control a short circuit between the first clock terminal and a second clock terminal.

公开(公告)号：US20240071314A1

公开(公告)日：2024-02-29

申请号：US18217924

申请日：2023-07-03

Applicant: Samsung Display Co., Ltd.

Inventor： Nackhyeon Keum ,  Kimyeong Eom ,  Kwangsae Lee

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2330/021

Abstract: Provided is a gate driver including a plurality of stages, wherein each stage includes an output unit including a pull-up transistor and a pull-down transistor, and a second node controller configured to control a voltage of a second control node to which a gate of the pull-up transistor is connected, wherein the second node controller includes a first control transistor connected between the first clock terminal and the second control node and including a gate connected to the first control node, and a second control transistor including a gate connected to the gate of the first control transistor and configured to control a short circuit between the first clock terminal and a second clock terminal.

公开(公告)号：US11493552B2

公开(公告)日：2022-11-08

申请号：US17191581

申请日：2021-03-03

Applicant: Samsung Display Co., Ltd.

Inventor： Hwayoung Song ,  Seungwoo Sung ,  Dong Eup Lee ,  Seungji Cha ,  Kimyeong Eom ,  Kwangsae Lee

IPC: G01R31/317 ,  G09G3/20

Abstract: A display panel test circuit includes a first transistor connected to a first data line and receiving a red lighting test signal, a second transistor connected to the first data line and receiving a blue lighting test signal, a third transistor connected to a second data line and receiving a first green lighting test signal, a fourth transistor connected to a third data line and receiving the red lighting test signal, a fifth transistor connected to the third data line and receiving the blue lighting test signal, a sixth transistor connected to a fourth data line and receiving a second green lighting test signal, a seventh transistor connected to the second data line and receiving a crack test signal, and an eighth transistor connected to the fourth data line and receiving the crack test signal. The display panel test circuit performs one or more tests on a display panel.

公开(公告)号：US11355568B2

公开(公告)日：2022-06-07

申请号：US16542850

申请日：2019-08-16

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Ji-Hyun Ka ,  Taegeun Kim ,  Ki Myeong Eom ,  Kwangsae Lee

IPC: H01L27/32 ,  H01L27/12 ,  H01L21/44 ,  H01L29/786 ,  H01L29/423 ,  H01L29/417

Abstract: An organic light emitting diode (“OLED”) display device includes a substrate having a display region including a light emitting region and a peripheral region, and a pad region located in one side of the display region, a plurality of light emitting structures on the substrate in the light emitting region, and a plurality of fan-out wirings including a low fan-out wiring in the peripheral region on the substrate, a middle fan-out wiring on the low fan-out wiring, the middle fan-out wiring overlapping at least a portion of the low fan-out wiring, and an upper fan-out wiring on the middle fan-out wiring, the upper fan-out wiring overlapping at least a portion of the low fan-out wiring.

公开(公告)号：US10964771B2

公开(公告)日：2021-03-30

申请号：US16426049

申请日：2019-05-30

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Minku Lee ,  Jihyun Ka ,  Kwangsae Lee

IPC: H01L27/32 ,  G09G3/3225

Abstract: A display panel including a substrate including a display area surrounding an opening area and a non-display area between the opening area and the display area; a plurality of display elements on the display area; a plurality of scan lines extending in a first direction and detouring around an edge of the opening area; a plurality of data lines extending in a second direction that intersects with the first direction, the plurality of data lines detouring around the edge of the opening area; and a plurality of emission control lines extending in the first direction and detouring around the edge of the opening area.