公开(公告)号：US09842557B2

公开(公告)日：2017-12-12

申请号：US14961672

申请日：2015-12-07

Applicant: Samsung Display Co., Ltd.

Inventor： Jonghee Kim ,  Youngwan Seo ,  Jaekeun Lim

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3677 ,  G09G2310/0286 ,  G11C19/287

Abstract: A gate driving circuit provides a plurality of gate lines of a display panel with gate signals, the gate driving circuit including: a plurality of driving stages which correspond to the plurality of gate lines, respectively, and each of which outputs a carry signal and a gate signal for driving a corresponding gate line in response to a clock signal, an input signal, and a carry signal of a next stage; and a dummy driving stage which outputs a dummy carry signal in response to the clock signal, a carry signal of the last stage of the plurality of driving stages, and a carry signal output from any one of the plurality of driving stages.

公开(公告)号：US20160218707A1

公开(公告)日：2016-07-28

申请号：US15006000

申请日：2016-01-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Junhyun Park ,  Jonghee Kim ,  Sunghwan Kim ,  Jaekeun Lim ,  Chongchul Chai

IPC: H03K17/687 ,  G09G3/36

Abstract: A gate driving circuit includes a plurality of driving stages, wherein an ith (where i is a natural number of 2 or more) driving stage among the plurality of driving stages includes: a output unit outputting an ith output signal including a high voltage generated based on a clock signal in response to a low voltage at a Q-node; a stabilization unit providing the low voltage to the Q-node in response to a switching signal applied to an A-node after the ith output signal is outputted; and an inverter unit outputting the switching signal for controlling the stabilization unit to the A-node.

Abstract translation: 栅极驱动电路包括多个驱动级，其中，所述多个驱动级中的第i个（其中i是2或更多的自然数）驱动级包括：输出单元，输出包括基于高电压的基于 响应于Q节点处的低电压的时钟信号; 稳定单元，响应于在输出第i个输出信号之后施加到A节点的切换信号，向Q节点提供低电压; 以及逆变器单元，输出用于将稳定单元控制到A节点的切换信号。

公开(公告)号：US12190791B2

公开(公告)日：2025-01-07

申请号：US18143011

申请日：2023-05-03

Applicant: Samsung Display Co., Ltd.

Inventor： Hyuk Kim ,  Jonghee Kim ,  Doo-Young Lee ,  Chang-Soo Lee ,  Sang-Uk Lim ,  Boyong Chung

IPC: G09G3/32 ,  H01L27/12

Abstract: Provided is a gate driving circuit comprising an N-th stage and an N+1-th stage. The N-th stage outputs an N-th scan gate signal based on an N-th scan clock signal, a voltage of a QN node, and a voltage of a QBN node and to output an N-th carry signal based on an N-th carry clock signal, the voltage of the QN node, and the voltage of the QBN node. The N+1-th stage outputs an N+1-th scan gate signal based on an N+1-th scan clock signal, a voltage of a QN+1 node, and the voltage of the QBN node and an N+1-th carry signal based on an N+1-th carry clock signal, the voltage of the QN+1 node, and the voltage of the QBN node. The N-th stage and the N+1-th stage share an inverting circuit. The inverting circuit controls the QBN node based on a third signal. N is a positive integer.

公开(公告)号：US11710453B2

公开(公告)日：2023-07-25

申请号：US17490153

申请日：2021-09-30

Applicant: Samsung Display Co., LTD.

Inventor： Chang-Soo Lee ,  Boyong Chung ,  Jonghee Kim

IPC: G09G3/3241 ,  G09G3/3291

CPC classification number: G09G3/3241 ,  G09G3/3291 ,  G09G2300/0842

Abstract: A pixel circuit including an organic light emitting diode, a first transistor configured to drive the organic light emitting diode, a second transistor electrically connected between a gate node of the first transistor and a data line, a third transistor electrically connected between a source node of the first transistor and an initialization voltage line and a storage capacitor electrically connected between the gate node and the source node of the first transistor. In a data writing period in which the storage capacitor is charged with electric charges, a turn-off time of the third transistor lags compared to a turn-off time of the second transistor.

公开(公告)号：US20220130334A1

公开(公告)日：2022-04-28

申请号：US17490153

申请日：2021-09-30

Applicant: Samsung Display Co., LTD.

Inventor： Chang-Soo LEE ,  Boyong Chung ,  Jonghee Kim

IPC: G09G3/3241 ,  G09G3/3291

Abstract: A pixel circuit including an organic light emitting diode, a first transistor configured to drive the organic light emitting diode, a second transistor electrically connected between a gate node of the first transistor and a data line, a third transistor electrically connected between a source node of the first transistor and an initialization voltage line and a storage capacitor electrically connected between the gate node and the source node of the first transistor. In a data writing period in which the storage capacitor is charged with electric charges, a turn-off time of the third transistor lags compared to a turn-off time of the second transistor.

公开(公告)号：US10789906B2

公开(公告)日：2020-09-29

申请号：US15006000

申请日：2016-01-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Junhyun Park ,  Jonghee Kim ,  Sunghwan Kim ,  Jaekeun Lim ,  Chongchul Chai

IPC: G11C19/00 ,  G09G3/36 ,  G11C19/28

Abstract: A gate driving circuit includes a plurality of driving stages, wherein an ith (where i is a natural number of 2 or more) driving stage among the plurality of driving stages includes: a output unit outputting an ith output signal including a high voltage generated based on a clock signal in response to a low voltage at a Q-node; a stabilization unit providing the low voltage to the Q-node in response to a switching signal applied to an A-node after the ith output signal is outputted; and an inverter unit outputting the switching signal for controlling the stabilization unit to the A-node.

公开(公告)号：US09741306B2

公开(公告)日：2017-08-22

申请号：US14835573

申请日：2015-08-25

Applicant: Samsung Display Co., Ltd.

Inventor： Ji-Sun Kim ,  Jonghee Kim ,  Youngwan Seo ,  Jaekeun Lim ,  Chongchul Chai

IPC: G09G3/36

CPC classification number: G09G3/3648 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2320/0219

Abstract: According to an embodiment, a display device includes a display panel including a plurality of pixels respectively connected to a plurality of gate lines and a plurality of data lines, a gate driver driving the plurality of gate lines, a data driver configured to output a plurality of data output signals to the plurality of data lines in response to a data signal, a demultiplexer circuit configured to provide the plurality of data output signals to the plurality of data lines in response to a first selection signal and a second selection signal; and a timing controller configured to provide the data signal to the data driver, outputting the first selection signal and the second selection signal, and controlling the gate driver.

公开(公告)号：US20230169926A1

公开(公告)日：2023-06-01

申请号：US17980425

申请日：2022-11-03

Applicant: Samsung Display Co., Ltd.

Inventor： Jonghee Kim ,  Bogyeong Kim ,  Dooyoung Lee ,  Takyoung Lee ,  Sanguk Lim ,  BoYong Chung

IPC: G09G3/3266 ,  G09G3/3233

CPC classification number: G09G3/3266 ,  G09G3/3233 ,  G09G2300/0842 ,  G09G2310/08 ,  G09G2310/0286 ,  G09G2320/041 ,  G09G2320/045 ,  G09G2320/0233

Abstract: A scan driver includes stages, and first to third clock signals are applied to the stages, respectively. A falling time of the first clock signal is shorter than falling times of the second and third clock signals.

公开(公告)号：US10186198B2

公开(公告)日：2019-01-22

申请号：US14834015

申请日：2015-08-24

Applicant: Samsung Display Co., Ltd.

Inventor： Jonghee Kim ,  Youngwan Seo ,  Jaekeun Lim ,  Chongchul Chai

IPC: G09G3/32 ,  G09G3/3258 ,  G09G3/3291 ,  G09G3/36

Abstract: A gate driving circuit includes a first driving stage driving a first gate line included in a display panel. The first driving stage includes a first output transistor outputting a first carry signal on the basis of a first clock signal in response to a voltage of a first node, a second output transistor outputting a first gate signal on the basis of the first clock signal in response to the voltage of the first node, a first control transistor applying a second clock signal to a second node, a second control transistor applying a start signal to the first node in response to a voltage of the second node, and a third control transistor applying a first discharge voltage to the first node in response to the first carry signal.

公开(公告)号：US10096294B2

公开(公告)日：2018-10-09

申请号：US15478446

申请日：2017-04-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jonghee Kim ,  Kyoungju Shin

IPC: G09G3/36

Abstract: A gate driving circuit includes multiple stages to provide gate signals to gate lines of a display panel. At least one stage includes first and second input circuits and output circuit, discharge circuit, pull down circuit, and hold circuit. The first input circuit delivers a (k−2)th gate signal to a first node. A second input circuit delivers a (k+1)th gate signal to the first node. The output circuit outputs a first clock signal as a k-th gate signal based on the first node. The discharge circuit discharges a second node based on the (k−2)th gate signal. The pull down circuit discharges the first node based on the second node and (k+2)th gate signal and discharges the k-th gate signal based on the second node and a (k+2)th gate signal. The hold circuit delivers a (k+3)th gate signal to the second node and maintains the signal level of the second node.