Display device and driving method thereof

    公开(公告)号:US11620927B2

    公开(公告)日:2023-04-04

    申请号:US17460779

    申请日:2021-08-30

    Abstract: A display device includes a scale factor provider, a grayscale converter, and pixels. The scale factor provider calculates an n-th scale factor based on n-th input grayscales received during an n-th frame period. The grayscale converter calculates (n+p)th output grayscales by applying the n-th scale factor to (n+p)th input grayscales received during an (n+p)th frame period in a first mode. The pixels output light to display an image based on the (n+p)th output grayscales, where n is an integer greater than 0 and p is an integer greater than 1.

    Display device and driving method thereof

    公开(公告)号:US11043156B2

    公开(公告)日:2021-06-22

    申请号:US16861926

    申请日:2020-04-29

    Abstract: A display device includes a display panel, a power supply, a signal controller configured to generate first and second clock signals having a period, a clock signal generator configured to generate a gate clock signal that is raised to a high level voltage in synchronization with the first clock signal, and that falls to a low level voltage in synchronization with the second clock signal, generate a panel separation signal by comparing a voltage of the gate clock signal with a first reference voltage during a falling period during which the gate clock signal falls, and transfer the panel separation signal to the power supply or the signal controller, and a gate driver configured to sequentially apply a gate signal by using the gate clock signal, wherein the power supply or the signal controller is configured to stop outputting depending on the panel separation signal.

    Display device
    19.
    发明授权

    公开(公告)号:US11501691B2

    公开(公告)日:2022-11-15

    申请号:US16917740

    申请日:2020-06-30

    Abstract: A display device may include a timing controller, a level shifter, a gate driver, and a display panel. The timing controller may generate a first on-clock signal, a first off-clock signal, and a first output control signal. The level shifter may generate a first-type gate clock signal. A rising edge of the first-type gate clock signal and a falling edge of the first-type gate clock signal may be respectively synchronized with a rising edge of the first on-clock signal and a falling edge of the first off-clock signal. The gate driver may output first-type gate signals based on the first-type gate clock signal. The display panel may include pixels. The pixels may emit lights in response to the first-type gate signals. The level shifter may partially block a pulse of the first-type gate clock signal based on the first output control signal to generate sub-pulses.

    Display device and driving method thereof

    公开(公告)号:US11270641B1

    公开(公告)日:2022-03-08

    申请号:US17236481

    申请日:2021-04-21

    Abstract: A display device includes a first power source, a timing controller, and pixels. The timing controller is connected to the first power source through a main line, an auxiliary line, and a detection line. The pixels are commonly connected to the first power source through a first power line. The first power source includes: a main power source connected to the first power line and the main line; an auxiliary power source connected to the auxiliary line; a rectifier connected between the auxiliary power source and the first power line; and a comparator comparing a voltage of the first power line and providing its output to the detection line.

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