公开(公告)号：US20230335062A1

公开(公告)日：2023-10-19

申请号：US18128956

申请日：2023-03-30

Applicant: Samsung Display Co., Ltd.

Inventor： Haijung In ,  Chulkyu Kang ,  Kimyeong Eom ,  Soongi Kwon ,  Minjeong Kim

IPC: G09G3/3266 ,  G09G3/3258

CPC classification number: G09G3/3266 ,  G09G3/3258 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0223

Abstract: A scan driver includes a stage, wherein the stage includes: a first output controller including a first pull-up transistor and a first pull-down transistor, wherein the first pull-up transistor has a gate connected to a first control node, and the first pull-down transistor has a gate connected to a second control node; a second output controller including a second pull-up transistor and a second pull-down transistor, wherein the second pull-up transistor has a gate connected to the first control node, and the second pull-down transistor has a gate connected to the second control node; and a stabilizer configured to maintain the first control node at an off-voltage level based on the second control node being at an on-voltage level.

公开(公告)号：US20230140806A1

公开(公告)日：2023-05-04

申请号：US17748926

申请日：2022-05-19

Applicant: Samsung Display Co., Ltd.

Inventor： Haijung In ,  Chulkyu Kang ,  Soongi Kwon ,  Minjeong Kim ,  Kimyeong Eom

IPC: G09G3/3258

Abstract: A driver includes a stage that includes a first controller, a second controller, and a first output unit. The first controller controls a voltage level of a first node. The second controller controls voltage levels of a second node and a third node to be equal to the voltage level of a first node or an opposite voltage level of the voltage level of the first node, and controls a voltage level of a fifth node to be equal to the opposite voltage level of the voltage level of the first node. The first output unit may output a gate control signal, which has a first voltage when the second node and the third node is in an on-voltage level state, and has a second voltage when the fifth node is in an on-voltage level state.

公开(公告)号：US11348989B2

公开(公告)日：2022-05-31

申请号：US16909032

申请日：2020-06-23

Applicant: Samsung Display Co., Ltd.

Inventor： Kwangsae Lee ,  Ji-Hyun Ka ,  Kimyeong Eom

IPC: H01L27/32 ,  H01L51/00

Abstract: An electronic panel including: a base substrate including a first area and a second area, wherein the first area includes a module area and a display area adjacent to the module area; a display element layer including a plurality of display elements, wherein the plurality of display elements overlaps the first area; an encapsulation layer configured to cover the display elements; sensing patterns overlapping the first area and disposed on the encapsulation layer; a crack sensing pattern overlapping the module area and disposed on the encapsulation layer; an auxiliary pattern overlapping the module area and disposed on the encapsulation layer, wherein the auxiliary pattern has a shape that extends along an edge of the crack sensing pattern and extends between the sensing patterns and the crack sensing pattern; and a signal line disposed on the encapsulation layer to electrically connect the crack sensing pattern to the auxiliary pattern.

公开(公告)号：US12165553B2

公开(公告)日：2024-12-10

申请号：US18095097

申请日：2023-01-10

Applicant: Samsung Display Co., LTD.

Inventor： Hai-Jung In ,  Chulkyu Kang ,  Kimyeong Eom ,  Soon-Gi Kwon ,  Min Jeong Kim

IPC: G09G3/20

Abstract: A gate driver includes: a pull-up circuit configured to pull up a gate output signal to a high voltage in response to a signal at a first node of the pull-up circuit; a first pull-down circuit configured to pull down the gate output signal to a low voltage in response to a signal at a second node of the first pull-down circuit; a second pull-down circuit configured to pull down the gate output signal to the low voltage in response to a signal at a third node of the second pull-down circuit; a first selection circuit configured to activate the first pull-down circuit and deactivate the second pull-down circuit based on a first selection signal; and a second selection circuit configured to activate the second pull-down circuit and deactivate the first pull-down circuit based on a second selection signal.

公开(公告)号：US12073791B2

公开(公告)日：2024-08-27

申请号：US17748926

申请日：2022-05-19

Applicant: Samsung Display Co., Ltd.

Inventor： Haijung In ,  Chulkyu Kang ,  Soongi Kwon ,  Minjeong Kim ,  Kimyeong Eom

IPC: G09G3/3258

CPC classification number: G09G3/3258 ,  G09G2300/0426 ,  G09G2310/08

Abstract: A driver includes a stage that includes a first controller, a second controller, and a first output unit. The first controller controls a voltage level of a first node. The second controller controls voltage levels of a second node and a third node to be equal to the voltage level of a first node or an opposite voltage level of the voltage level of the first node, and controls a voltage level of a fifth node to be equal to the opposite voltage level of the voltage level of the first node. The first output unit may output a gate control signal, which has a first voltage when the second node and the third node is in an on-voltage level state, and has a second voltage when the fifth node is in an on-voltage level state.

公开(公告)号：US11587513B2

公开(公告)日：2023-02-21

申请号：US17321825

申请日：2021-05-17

Applicant: Samsung Display Co., Ltd.

Inventor： Hai-Jung In ,  Kimyeong Eom ,  Ji-Hyun Ka

IPC: G09G3/3291

Abstract: An emission driver includes a plurality of stages. A stage of the plurality of stages receives a start signal, a first clock signal, a second clock signal, a protection signal, a first gate power voltage and a second gate power voltage and outputs an emission signal. The stage of the plurality of stages includes a pull-up switching element connected between a first gate power voltage terminal which receives the first gate power voltage and an emission signal output terminal which outputs the emission signal, a pull-down switching element connected between a second gate power voltage terminal which receives the second gate power voltage and the emission signal output terminal and a protection switching element which applies the first gate power voltage to a control electrode of the pull-down switching element in response to the protection signal.

公开(公告)号：US11574594B2

公开(公告)日：2023-02-07

申请号：US17199851

申请日：2021-03-12

Applicant: Samsung Display Co., Ltd.

Inventor： Ji-Hyun Ka ,  Nackhyeon Keum ,  Kimyeong Eom

IPC: G09G3/3258 ,  G09G3/3291 ,  G09G3/3266

Abstract: A display panel of an OLED display device includes a first pixel configured to emit first color light, a second pixel configured to emit second color light, and a third pixel configured to emit third color light. Each of the first, second and third pixels includes at least two transistors, at least one capacitor and an organic light emitting diode. At least one of at least two transistors or at least one capacitor included in the third pixel has a size different from a size of a corresponding one at least two transistors or at least one capacitor included in the first pixel or the second pixel.

公开(公告)号：US20210057505A1

公开(公告)日：2021-02-25

申请号：US16909032

申请日：2020-06-23

Applicant: Samsung Display Co., Ltd.

Inventor： Kwangsae Lee ,  Ji-Hyun Ka ,  Kimyeong Eom

IPC: H01L27/32 ,  H01L51/00

Abstract: An electronic panel including: a base substrate including a first area and a second area, wherein the first area includes a module area and a display area adjacent to the module area; a display element layer including a plurality of display elements, wherein the plurality of display elements overlaps the first area; an encapsulation layer configured to cover the display elements; sensing patterns overlapping the first area and disposed on the encapsulation layer; a crack sensing pattern overlapping the module area and disposed on the encapsulation layer; an auxiliary pattern overlapping the module area and disposed on the encapsulation layer, wherein the auxiliary pattern has a shape that extends along an edge of the crack sensing pattern and extends between the sensing patterns and the crack sensing pattern; and a signal line disposed on the encapsulation layer to electrically connect the crack sensing pattern to the auxiliary pattern.

公开(公告)号：US09748321B2

公开(公告)日：2017-08-29

申请号：US15190101

申请日：2016-06-22

Applicant: Samsung Display Co., Ltd.

Inventor： Dongsoo Kim ,  Jinwoo Park ,  Changsoo Pyon ,  Junwon Choi ,  Juhee Hyeon ,  Wonkyu Kwak ,  Kimyeong Eom

IPC: H01L27/12 ,  H01L27/32 ,  G09G3/3233

CPC classification number: H01L27/3262 ,  G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/0262 ,  H01L27/3272

Abstract: An organic light-emitting diode display is disclosed. In one aspect, the display includes a substrate that includes a first sub-pixel region and a second sub-pixel region adjacent to the first sub-pixel region, and a first driving circuit and a second driving circuit respectively disposed in the first sub-pixel region and the second sub-pixel region. The first and second driving circuits include a first thin film transistor (TFT) and a second TFT. The display further includes a first pixel electrode and a second pixel electrode electrically connected to the first driving circuit and the second driving circuit, respectively, and a common electrode facing the first and second pixel electrodes. A first organic emission layer is interposed between the first pixel electrode and the common electrode, and a second organic emission layer interposed between the second pixel electrode and the common electrode, and a light-shielding member is configured to shield incident light.

公开(公告)号：US12100355B2

公开(公告)日：2024-09-24

申请号：US18217924

申请日：2023-07-03

Applicant: Samsung Display Co., Ltd.

Inventor： Nackhyeon Keum ,  Kimyeong Eom ,  Kwangsae Lee

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2330/021

Abstract: Provided is a gate driver including a plurality of stages, wherein each stage includes an output unit including a pull-up transistor and a pull-down transistor, and a second node controller configured to control a voltage of a second control node to which a gate of the pull-up transistor is connected, wherein the second node controller includes a first control transistor connected between the first clock terminal and the second control node and including a gate connected to the first control node, and a second control transistor including a gate connected to the gate of the first control transistor and configured to control a short circuit between the first clock terminal and a second clock terminal.