公开(公告)号：US10119074B2

公开(公告)日：2018-11-06

申请号：US15421848

申请日：2017-02-01

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Ji Eun Jang ,  Sun Young Kwon ,  Tae Hoon Kim ,  Jong Ho Son ,  Keun Chan Oh ,  Won Gap Yoon ,  Gak Seok Lee ,  Jin Hyeong Lee ,  Chang Hun Lee

IPC: G02F1/1333 ,  C09K19/34 ,  C07D307/83 ,  G02F1/1337 ,  G02F1/1343

Abstract: A liquid crystal composition includes a compound having a structure represented by formula A-1: wherein RA1 is an alkyl group, an alkoxy group, a cyano group, a halogen atom, or a hydrogen atom, RA2 is an alkyl group, a cyano group, a halogen atom, or a hydrogen atom, ZA is *—O—*, *—COO—*, *—OCO—*, *—CF2O—*, *—OCF2—*, *—CH2O—*, *—OCH2—*, *—SCH2—*, *—CH2S—*, *—C2F4—*, *—CH2CF2—*, *—CF2CH2—*, *—(CH2)k—*, *—CH═CH—*, *—CF═CF—*, *—CH═CF—*, *—CF═CH—*, *—C≡C—*, *—CH═CHCH2O—*, or a single bond, X is a halogen atom, each of l1 and l2 is independently an integer of 0 to 2, and when l1 is 2 and ZA in a repeating unit defined by l1 are the same or different, wherein k is an integer of 1 to 5 and “*” indicates a point of attachment.

公开(公告)号：US10007132B2

公开(公告)日：2018-06-26

申请号：US14700984

申请日：2015-04-30

Applicant: Samsung Display Co., Ltd.

Inventor： Won Gap Yoon ,  Ji Eun Jang ,  Kyung Seon Tak ,  Keun Chan Oh

IPC: G02F1/1333 ,  G02F1/13 ,  H01L27/12

CPC classification number: G02F1/1333 ,  G02F1/1309 ,  H01L27/1218

Abstract: Provided are a display panel and a thin film transistor array substrate. According to one or more exemplary embodiments, a display panel includes: a first substrate including a pixel area and a non-pixel area; a second substrate that faces the first substrate; and a crack guide groove disposed on a surface of at least one of the first substrate and the second substrate.

公开(公告)号：US09984641B2

公开(公告)日：2018-05-29

申请号：US15158471

申请日：2016-05-18

Applicant: Samsung Display Co., Ltd.

Inventor： Sung In Kang ,  Kyun Ho Kim ,  Min Ho Park ,  Ji Eun Jang

IPC: G09G3/20 ,  G09G3/36 ,  G09G3/3266

CPC classification number: G09G3/3677 ,  G09G3/20 ,  G09G3/3266 ,  G09G3/3674 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/0267 ,  G09G2320/0219 ,  G09G2330/04 ,  G09G2330/06 ,  G09G2330/08 ,  G09G2330/12

Abstract: A gate protection circuit includes: a clock signal generator to generate a plurality of gate clock signals; a gate driver to output gate signals based on the plurality of gate clock signals, the gate driver including a plurality of gate driving circuits cascaded to each other; and a monitoring line configured to transmit a feedback signal based on the plurality of gate clock signals via the plurality of gate driving circuits to the clock signal generator. The clock signal generator is to block generation of the plurality of gate clock signals in response to the feedback signal.