公开(公告)号：US10482823B2

公开(公告)日：2019-11-19

申请号：US15852773

申请日：2017-12-22

Applicant: Samsung Display Co., Ltd.

Inventor： Wonjun Lee ,  Gichang Lee ,  Cholho Kim ,  Gunwoo Yang

IPC: G09G3/3266 ,  G09G3/3291 ,  G09G3/20 ,  G09G3/3233

Abstract: A light emitting display device includes: a first switch connected between a data line and a first node and including a gate connected to a first scan line; a second switch connected between a first driving power line and a second node and including a gate electrode connected to the first node; a first capacitor connected between the first node and the second node; a light emitting element connected between the second node and a second driving power line; a scan driver applying a first A-scan signal and a first B-scan signal during different times to the first scan line; a data driver applying a first initialization signal and a data signal to the data line at different times; and a power supply portion applying a first driving voltage, a second driving voltage, and a third driving voltage to the first driving power line at different times.

公开(公告)号：US10185189B2

公开(公告)日：2019-01-22

申请号：US15055323

申请日：2016-02-26

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jihoon Yang ,  Myeongeon Kim ,  Cholho Kim ,  Keumdong Jung ,  Hyunyoung Choi

IPC: G02F1/1343 ,  G02F1/1362 ,  H01L27/12 ,  G02F1/1339

Abstract: A display device includes: a gate transmission wiring; a gate insulating layer disposed on the gate transmission wiring; and a pixel electrode and a data transmission wiring that are disposed on the gate insulating layer. When a gate signal voltage is applied to the gate transmission wiring, the gate transmission wiring may serve as a gate electrode that activates a semiconductor layer. In addition, when such a gate signal voltage is not applied thereto, the gate transmission wiring may form an electric field by a voltage difference between the gate transmission wiring and the pixel electrode, to thereby control a liquid crystal layer.

公开(公告)号：US10108061B2

公开(公告)日：2018-10-23

申请号：US15134869

申请日：2016-04-21

Applicant: Samsung Display Co., Ltd.

Inventor： Keumdong Jung ,  Daecheol Kim ,  Seongyoung Lee ,  Cholho Kim ,  Jihoon Yang ,  Hyunyoung Choi

IPC: G02F1/1343 ,  G02F1/1362 ,  G02F1/1333 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/417 ,  H01L29/94 ,  H01L31/10

Abstract: A thin-film transistor (TFT) array substrate includes a transistor disposed on a base substrate and a storage capacitor electrically connected to the transistor. The transistor includes a gate electrode, an active layer electrically insulated from the gate electrode, the active layer including a semiconductor material, and a first electrode and a second electrode disposed to be spaced apart from each other on the active layer. The storage capacitor includes a lower electrode including a light inflow path, and an upper electrode disposed to face the lower electrode and electrically connected to the second electrode.

公开(公告)号：US11538422B2

公开(公告)日：2022-12-27

申请号：US17463518

申请日：2021-08-31

Applicant: Samsung Display Co., LTD.

Inventor： Wonjun Lee ,  Mihyeon Jo ,  Cholho Kim

IPC: G09G3/3291 ,  G09G3/3266 ,  G09G3/3233

Abstract: A pixel of a light emitting display device includes: a switching transistor which transfers a data voltage in response to a gate writing signal, a storage capacitor which stores a storage voltage, a driving transistor which generates a driving current based on the storage voltage stored in the storage capacitor, an emission transistor which selectively forms a path of the driving current in response to an emission signal, a light emitting diode which emits light based on the driving current, and a diode initialization transistor which transfers an initialization voltage to the light emitting diode in response to the emission signal. The storage voltage corresponds to a value obtained by subtracting a threshold voltage of the driving transistor from the data voltage.

公开(公告)号：US10755645B2

公开(公告)日：2020-08-25

申请号：US16351136

申请日：2019-03-12

Applicant: Samsung Display Co., Ltd.

Inventor： Hyo-Chul Lee ,  Cholho Kim ,  Hongbo Kim ,  Yoonjung Chai

IPC: G09G3/3266

Abstract: A scan driver includes: a blocking circuit configured to receive a scan control signal and to block the scan control signal lower than a predetermined first reference voltage and higher than a predetermined second reference voltage, wherein the second reference voltage is higher than the first reference voltage; and a plurality of stages configured to output scan signals in response to the scan control signal, wherein the blocking circuit includes: a first block circuit configured to block the scan control signal lower than the first reference voltage; and a second block circuit configured to block the scan control signal higher than the second reference voltage.

公开(公告)号：US10607547B2

公开(公告)日：2020-03-31

申请号：US16205499

申请日：2018-11-30

Applicant: Samsung Display Co., Ltd.

Inventor： Gunwoo Yang ,  Cholho Kim ,  Wonjun Lee

IPC: G09G3/3258 ,  G09G3/3233

Abstract: A display apparatus includes a voltage generator which generates an initial controlling signal which comprises a high voltage, a middle voltage and a low voltage, where the initial controlling signal swings from the middle voltage to the low voltage after a plurality of gate signals is simultaneously dropped from a high voltage to a low voltage thereof.

公开(公告)号：US10255845B2

公开(公告)日：2019-04-09

申请号：US15447748

申请日：2017-03-02

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Cholho Kim ,  Gunwoo Yang ,  Jihoon Yang ,  Yongwoo Lee ,  Hyunyoung Choi

IPC: G09G3/20

Abstract: An N-th stage of a gate driver includes a first control circuit, a gate signal generating circuit, a carry signal generating circuit, a second control circuit, a third control circuit, and a holding circuit. The first control circuit controls a first signal in response to a first input signal. The gate signal generating circuit generates a gate signal in response to a clock signal and the first signal. The carry signal generating circuit generates a carry signal in response to the clock signal and the first signal. The second control circuit controls the first signal in response to a second input signal. The third control circuit generates a hold control signal in response to a third input signal having a frequency lower than the clock signal's. The holding circuit maintains levels of the first signal, the gate signal, and the carry signal in response to the hold control signal.