-
公开(公告)号：US20210041727A1
公开(公告)日：2021-02-11
申请号：US17083525
申请日：2020-10-29
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Stephane Monfray , Frédéric Boeuf
Abstract: A photonic device includes a first region having a first doping type, and a second region having a second doping type, where the first region and the second region contact to form a vertical PN junction. The first region includes a silicon germanium (SiGe) region having a gradual germanium concentration.
-
公开(公告)号：US10823986B2
公开(公告)日：2020-11-03
申请号：US16254798
申请日：2019-01-23
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Stephane Monfray , Frédéric Boeuf
Abstract: A photonic device includes a first region having a first doping type, and a second region having a second doping type, where the first region and the second region contact to form a vertical PN junction. The first region includes a silicon germanium (SiGe) region having a gradual germanium concentration.
-
公开(公告)号：US20180329140A1
公开(公告)日：2018-11-15
申请号：US16029365
申请日：2018-07-06
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Frédéric Boeuf , Charles Baudot
CPC classification number: G02B6/12004 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L24/13 , H01L24/14 , H01L25/043 , H01L2924/00014 , H01L2924/10252 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H02S40/44 , H01L2224/13099
Abstract: A method for making an electro-optic device includes forming a first photonic device having a first material in a first photonic layer over a substrate layer. A second photonic layer with a second photonic device is formed over the first photonic layer and includes a second material different than the first material. A dielectric layer is formed over the second photonic layer. A first electrically conductive via extending through the dielectric layer and the second photonic layer is formed so as to couple to the first photonic device. A second electrically conductive via extending through the dielectric layer and coupling to the second photonic device is formed. A third electrically conductive via extending through the dielectric layer, the second photonic layer, and the first photonic layer is formed so as to couple to the substrate layer.
-
公开(公告)号：US09411176B2
公开(公告)日：2016-08-09
申请号：US14492435
申请日：2014-09-22
Applicant: STMICROELECTRONICS (CROLLES 2) SAS , STMICROELECTRONICS SA
Inventor： Jean-Robert Manouvrier , Frédéric Boeuf
CPC classification number: G02F1/025 , G02F1/225 , G02F2001/212
Abstract: An electro-optical phase shifter to be located in an optical waveguide may include a rib of a semiconductor material extending along a length of the optical waveguide and a control structure configured to modify a concentration of carriers in the rib according to a control voltage present between first and second control terminals of the phase shifter. The control structure may include a conductive layer covering a portion of the rib and electrically connected to a first of the control terminals. An insulating layer may be configured to electrically isolate the conductive layer from the rib.
Abstract translation: 位于光波导中的电光移相器可以包括沿着光波导的长度延伸的半导体材料的肋，以及控制结构，其被配置为根据存在于所述肋之间的控制电压来修改肋中的载流子的浓度 移相器的第一和第二控制端子。 控制结构可以包括覆盖肋的一部分并电连接到第一控制端的导电层。 绝缘层可以被配置为将导电层与肋电隔离。
-
公开(公告)号：US11686992B2
公开(公告)日：2023-06-27
申请号：US17476668
申请日：2021-09-16
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Frédéric Boeuf , Cyrille Barrera
CPC classification number: G02F1/2257 , G02F1/025 , G02F1/035 , G02F2202/103
Abstract: A capacitive electro-optical modulator includes a silicon layer having a cavity having sidewalls and a floor. A germanium or silicon-germanium strip overlies the silicon layer within the cavity. A silicon strip overlies the germanium or silicon-germanium strip within the cavity. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator fills the cavity laterally adjacent the germanium or silicon-germanium strip and the silicon strip and extending between the sidewalls of the cavity. An upper insulating layer overlies the silicon strip and the insulator. A layer of III-V material overlies the upper insulating layer. The layer of III-V material formed as a third strip is arranged facing the silicon strip and separated therefrom by a portion of the upper insulating layer.
-
Patent Agency Ranking
公开(公告)号：US11609378B2
公开(公告)日：2023-03-21
申请号：US17649520
申请日：2022-01-31
Inventor： Frédéric Boeuf , Luca Maggi
Abstract: A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.
-
公开(公告)号：US20190265519A1
公开(公告)日：2019-08-29
申请号：US16254798
申请日：2019-01-23
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Stephane Monfray , Frédéric Boeuf
IPC: G02F1/025
Abstract: A photonic device includes a first region having a first doping type, and a second region having a second doping type, where the first region and the second region contact to form a vertical PN junction. The first region includes a silicon germanium (SiGe) region having a gradual germanium concentration.
-
公开(公告)号：US10042115B2
公开(公告)日：2018-08-07
申请号：US15132408
申请日：2016-04-19
Applicant: STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Frédéric Boeuf , Charles Baudot
IPC: G02B6/12 , H01L23/48 , H01L23/00 , H01L21/768
Abstract: An electro-optic device may include a substrate layer, and a first photonic layer over the substrate layer and having a first photonic device. The electro-optic device may include a second photonic layer over the first photonic layer and having a second photonic device. The electro-optic device may include a dielectric layer over the second photonic layer, and a first electrically conductive via extending through the dielectric layer and the second photonic layer to couple to the first photonic device, and a second electrically conductive via extending through the dielectric layer and coupling to the second photonic device. The electro-optic device may include a third electrically conductive via extending through the substrate layer, the second photonic layer, and the first photonic layer to couple to the substrate layer.
-
公开(公告)号：US09891450B2
公开(公告)日：2018-02-13
申请号：US15084645
申请日：2016-03-30
Applicant: STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Charles Baudot , Maurin Douix , Frédéric Boeuf , Sébastien Cremer
CPC classification number: G02F1/025 , G02F2001/0151
Abstract: An E/O phase modulator may include a waveguide having an insulating substrate, a single-crystal silicon strip and a polysilicon strip of a same thickness and doped with opposite conductivity types above the insulating substrate, and an insulating interface layer between the single-crystal silicon strip and polysilicon strip. Each of the single-crystal silicon strip and polysilicon strip may be laterally continued by a respective extension, and a respective electrical contact coupled to each extension.
-
公开(公告)号：US12032265B2
公开(公告)日：2024-07-09
申请号：US18317705
申请日：2023-05-15
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Frédéric Boeuf , Cyrille Barrera
CPC classification number: G02F1/2257 , G02F1/025 , G02F1/035 , G02F2202/103
Abstract: A semiconductor device can be formed by etching a cavity in a first silicon layer that overlies an insulating layer, epitaxially growing a germanium or silicon-germanium layer in the cavity, epitaxially growing a second silicon layer in the cavity, etching the second silicon layer and the germanium or silicon-germanium layer to the floor of the cavity to define a first strip in the second silicon layer and a second strip in the germanium or silicon-germanium layer, selectively etching a portion of the second strip to decrease the width of the second strip, filling cavity portions arranged on either side of the first and second strips with an insulator, depositing an upper insulating layer over the first and second strips, and bonding a layer of III-V material to the upper insulating layer.
-
-
-
-
-
-
-
-
-
Search Results
24
records
(took 0.018 seconds)
