公开(公告)号：US10090827B2

公开(公告)日：2018-10-02

申请号：US15414419

申请日：2017-01-24

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Patrik Temleitner ,  Fady Abouzeid

IPC: H03K3/356 ,  H03K19/21

Abstract: A flip-flop includes a pulse-generator and a pulse-controlled latch. The pulse generator includes a first inverter to invert a clock signal, a second inverter to invert the inverted clock signal to generate a delayed clock signal, and a NOR gate having a first input coupled to an output of the first inverter, a second input coupled to the output of the second inverter, and an output, which, in operation, provides a pulse signal in response to a rising edge of a received clock signal. The pulse-controlled latch circuit has a data input and is controlled by the pulse signal and the delayed clock signal. The flip-flop may include a multiplexer to select an input signal.

公开(公告)号：US20140292374A1

公开(公告)日：2014-10-02

申请号：US14225520

申请日：2014-03-26

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Philippe Roche ,  Yvain Thonnart

IPC: H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/0016 ,  H01L27/0928 ,  H01L27/11807 ,  H01L27/1203 ,  H03K19/0013 ,  H03K19/01855 ,  H03K2217/0018

Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

Abstract translation: 一种用于控制具有逻辑单元和时钟树单元的IC的方法。 每个逻辑单元分别具有第一和第二FET，分别是pMOS和nMOS。 时钟树单元包括分别为pMOS和nMOS的第三和第四FET。 时钟树单元为逻辑单元提供时钟信号。 pMOS-FET的背栅电位差（“BGPD”）是其源电位减去其背栅电位之间的差异，反之亦然是nMOS-FET。 该方法包括将第一和第二后门电位差（BGPD）应用于逻辑单元的第一和第二FET，以及将第三BGPD应用于第三FET，其中第三BGPD为正并且大于施加的第一BGPD，其被应用 同时或将第四BGEPD应用于第四FET，其中第四BGPD为正并且大于并发应用的第二BGPD。

公开(公告)号：US10739807B2

公开(公告)日：2020-08-11

申请号：US16127771

申请日：2018-09-11

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Guenole Lallement ,  Fady Abouzeid

IPC: G05F3/20 ,  H03K19/0948 ,  H01L29/78 ,  H01L27/092 ,  H03K19/00 ,  G06F30/30

Abstract: A digital circuit includes logic circuitry formed by logic gates. Each logic gate includes a p-channel MOSFET and an n-channel MOSFET. A body bias generator circuit applies an n-body bias voltage to the n-body bias nodes of the p-channel MOSFETs and applies a p-body bias voltage to the p-body bias nodes of the n-channel MOSFETs. The body bias generator circuit operates in: a first mode to apply a ground supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply a positive supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage; and a second mode to apply the positive supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply the ground supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage.

公开(公告)号：US20180062652A1

公开(公告)日：2018-03-01

申请号：US15443779

申请日：2017-02-27

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fady Abouzeid ,  Gilles Gasiot

IPC: H03K19/003 ,  H03K3/356

Abstract: A storage element including two CMOS inverters, coupled head-to-tail between two nodes; and one MOS transistor, connected as a capacitor between said nodes.

公开(公告)号：US09479168B2

公开(公告)日：2016-10-25

申请号：US14225520

申请日：2014-03-26

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Philippe Roche ,  Yvain Thonnart

IPC: H03K19/096 ,  H03K19/00 ,  H01L27/092 ,  H01L27/118 ,  H01L27/12 ,  H03K19/0185

CPC classification number: H03K19/0016 ,  H01L27/0928 ,  H01L27/11807 ,  H01L27/1203 ,  H03K19/0013 ,  H03K19/01855 ,  H03K2217/0018

Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

Abstract translation: 一种用于控制具有逻辑单元和时钟树单元的IC的方法。 每个逻辑单元分别具有第一和第二FET，分别是pMOS和nMOS。 时钟树单元包括分别为pMOS和nMOS的第三和第四FET。 时钟树单元为逻辑单元提供时钟信号。 pMOS-FET的背栅电位差（“BGPD”）是其源电位减去其背栅电位之间的差异，反之亦然是nMOS-FET。 该方法包括将第一和第二后门电位差（BGPD）应用于逻辑单元的第一和第二FET，以及将第三BGPD应用于第三FET，其中第三BGPD为正并且大于施加的第一BGPD，其被应用 同时或将第四BGEPD应用于第四FET，其中第四BGPD为正并且大于并发应用的第二BGPD。