公开(公告)号：US20230380164A1

公开(公告)日：2023-11-23

申请号：US18116434

申请日：2023-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeonghoon Park ,  Inhwan Baek ,  Jaebok Baek ,  Jeehoon Han ,  Seungyoon Kim ,  Heesuk Kim ,  Byoungjae Park ,  Jongseon Ahn ,  Jumi Yun

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor memory device includes: a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure may include: a second substrate having a first region and a second region; a substrate insulating layer extending through the second substrate; a landing pad extending through the substrate insulating layer; gate electrodes, each having a gate pad region on the second region having an exposed upper surface; and a gate contact plug extending through the gate pad region of at least one of the gate electrodes and into the landing pad. The landing pad may include a pad portion that is surrounded by an internal side surface of the substrate insulating layer, and a via portion extending from the pad portion to the lower interconnection structure.

公开(公告)号：US11114461B2

公开(公告)日：2021-09-07

申请号：US16700059

申请日：2019-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongseon Ahn ,  Jaeryong Sim ,  Giyong Chung ,  Jeehoon Han

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/60 ,  H01L27/11573 ,  H01L29/06 ,  H01L21/311 ,  H01L27/1157

Abstract: A three-dimensional (3D) semiconductor memory device including: first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor lavers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structure.

公开(公告)号：US09799551B2

公开(公告)日：2017-10-24

申请号：US15016286

申请日：2016-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongseon Ahn

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033

CPC classification number: H01L21/76808 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816

Abstract: A method of manufacturing a semiconductor device may include forming an insulating layers on a substrate, forming a plurality of holes in an upper portion of the insulating layer, forming a mask layer having openings exposing at least a first set of the plurality of holes, etching a lower portion of the insulating layer exposed by one of the plurality of holes which is exposed by the mask layer to form a through hole in the insulating layer in combination with the one of the plurality of holes, and forming a conductive structure in the through hole.