-
公开(公告)号:US11646375B2
公开(公告)日:2023-05-09
申请号:US17112355
申请日:2020-12-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yunseong Lee , Jinseong Heo , Sangwook Kim , Taehwan Moon , Sanghyun Jo
IPC: H01L29/78 , H01L27/1159 , H01L29/51 , H01L21/02
CPC classification number: H01L29/78391 , H01L29/516 , H10B51/30 , H01L21/02181 , H01L21/02189
Abstract: Provided is a ferroelectric thin-film structure including a semiconductor substrate, a first ferroelectric layer on the semiconductor substrate, and a second ferroelectric layer on the semiconductor substrate. The second ferroelectric layer is spaced apart from the first ferroelectric layer and has a different dielectric constant from the first ferroelectric layer. The first ferroelectric layer and the second ferroelectric layer may be different from each other in terms of the amount of a dopant contained therein, and may exhibit different threshold voltages when applied to transistors.
-
公开(公告)号:US11522082B2
公开(公告)日:2022-12-06
申请号:US17001979
申请日:2020-08-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jinseong Heo , Sangwook Kim , Yunseong Lee , Sanghyun Jo , Hyangsook Lee
Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.
-
公开(公告)号:US11349026B2
公开(公告)日:2022-05-31
申请号:US16682380
申请日:2019-11-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yunseong Lee , Jinseong Heo , Sangwook Kim , Sanghyun Jo
IPC: H01L29/78 , H01L29/51 , H01L29/423 , H01L21/02 , H01L29/66 , H01L29/08 , H01L27/1159
Abstract: An electronic device includes a ferroelectric layer arranged on a channel region and a gate electrode arranged on the ferroelectric layer. The ferroelectric layer includes a plurality of first oxide monolayers and a second oxide monolayers that is arranged between the substrate and the gate electrode and include a material different from a material of the first oxide monolayers. The first oxide monolayers include oxide monolayers that are alternately formed and include materials different from one another.
-
公开(公告)号:US11132487B2
公开(公告)日:2021-09-28
申请号:US16856216
申请日:2020-04-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kyubin Han , Sangwook Kim
IPC: G06F30/392 , H01L21/033
Abstract: A layout of original pattern is rotated in a rotational direction to form a layout of rotation pattern. Vertices and segment points of the layout of rotation pattern are matched with ones of the reference points closest thereto, and the matched reference points are connected to form a layout of first modification pattern. A region of the layout of first modification pattern is enlarged to form a layout of second modification pattern. A layout of reference pattern having the same direction as the layout of rotation pattern is formed. A layout of target pattern is formed based on a region where the layouts of reference pattern and second modification pattern overlap. An optical proximity correction is performed on the layout of target pattern to form a layout of third modification pattern, which is rotated in a reverse rotational direction to form a layout of final pattern.
-
公开(公告)号:US10824043B2
公开(公告)日:2020-11-03
申请号:US16134614
申请日:2018-09-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junghyun Park , Sangwook Kim , Sunil Kim
Abstract: An optical modulation device and an apparatus including the same are provided. The optical modulation device may include a reflector, a nano-antenna array placed opposite to the reflector, and an active layer that is placed between the reflector and the nano-antenna array. The optical modulation device may further include a first insulating layer placed between the reflector and the active layer, a second insulating layer placed between the active layer and the nano-antenna array, and a wiring structure that electrically contacts the active layer. The wiring structure may be provided in at least one of a first place between the active layer and the first insulating layer and a second place between the active layer and the second insulating layer.
-
公开(公告)号:US10452349B2
公开(公告)日:2019-10-22
申请号:US15263539
申请日:2016-09-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sangwook Kim , Hyunseok Shin , Seungnyun Kim , Yongsang Yun , Changryong Heo
Abstract: The present disclosure provides an electronic device and methods for operating the electronic device. The electronic device may include: a housing having a coupling member removably attachable to an ear of a user; one or more microphones provided within the housing and configured to detect an external sound; at least one speaker provided within the housing; at least one communication circuit within the housing; a processor provided within the housing and electrically coupled to the one or more microphones, the at least one speaker, and the at least one communication circuit; and at least one memory provided within the housing, and electrically coupled to the processor. The memory may store instructions that cause, when executed, the processor to receive the detected external sound from the one or more microphones, to identify an direction of the external sound in relation to the user, to determine whether the direction of the external sound is within a predefined range, and to extract at least a portion of the external sound for further processing when the direction of the external sound is within the predefined range.
-
公开(公告)号:US09836220B2
公开(公告)日:2017-12-05
申请号:US14791714
申请日:2015-07-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sung-Won Jeong , Sangwook Kim , Joonwon Lee , Jinkyu Jeong , Hwanju Kim
CPC classification number: G06F3/061 , G06F3/0659 , G06F3/0688 , G06F12/0284 , G06F12/08 , G06F2212/1016
Abstract: A method of operating a data processing system includes transmitting process information indicating that a first process is classified as a critical process or a non-critical process to a kernel area, wherein the process information is generated in an application area, and the application area and the kernel area define a host. When the first process is classified as a critical process based on the process information, a first fastpath write signal is provided, using the kernel area, to a memory system to perform a fastpath write operation of first data for performing the first process. When the first process is classified as a non-critical process, a first slowpath write signal is provided to the memory system to perform a slowpath write operation of the first data. The fastpath write operation has a higher write speed than the slowpath write operation.
-
公开(公告)号:US12224346B2
公开(公告)日:2025-02-11
申请号:US18486493
申请日:2023-10-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jinseong Heo , Sangwook Kim , Yunseong Lee , Sanghyun Jo
Abstract: A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.
-
19.
公开(公告)号:US12210290B2
公开(公告)日:2025-01-28
申请号:US17497106
申请日:2021-10-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Pilsoo Kang , Sangwook Kim , Sanghun Kim
IPC: G06F30/398 , G03F1/36 , G03F7/00 , H01L21/027 , H01L21/033
Abstract: A method of fabricating a semiconductor device includes performing an optical proximity correction (OPC) operation on a layout and forming a photoresist pattern on a substrate using a photomask that is manufactured with the layout corrected by the OPC operation. The OPC operation includes sectioning the layout into a low-level patch and a high-level patch, performing a first OPC operation on the low-level patch, the first OPC operation including generating a first boundary correction pattern of a curvilinear shape on a boundary between the low-level patch and the high-level patch, performing a second OPC operation on the high-level patch, the second OPC operation including a second boundary correction pattern of a curvilinear shape on the boundary, and conforming the first boundary correction pattern and the second boundary correction pattern to each other to generate a conformed boundary correction pattern of a curvilinear shape.
-
公开(公告)号:US12191311B2
公开(公告)日:2025-01-07
申请号:US18529505
申请日:2023-12-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sangwook Kim , Jinseong Heo , Yunseong Lee , Sanghyun Jo
IPC: H01L29/786 , G06N3/063 , G06N3/08 , H01L27/12
Abstract: A semiconductor device includes a first transistor including a first channel layer of a first conductivity type, a second transistor provided in parallel with the first transistor and including a second channel layer of a second conductivity type, and a third transistor stacked on the first and second transistors. The third transistor may include a gate insulating film including a ferroelectric material. The third transistor may include third channel layer and a gate electrode that are spaced apart from each other in a thickness direction with the gate insulating film therebetween.
-
-
-
-
-
-
-
-
-