Abstract:
A semiconductor device includes a lower circuit pattern on a substrate, a common source plate (CSP) on the lower circuit pattern, a gate electrode structure including gate electrodes spaced apart from each other on the CSP in a first direction that is substantially perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction that is substantially parallel to the upper surface of the substrate, a first insulation pattern structure on a portion of the CSP that is adjacent to the gate electrode structure in the second direction, and a first division pattern extending on the CSP in a third direction that is substantially parallel to the upper surface of the substrate and that crosses the second direction, the first division pattern extending through a portion of the gate electrode structure that is adjacent to the first insulation pattern structure.
Abstract:
An electronic apparatus includes a memory configured to store a plurality of images; and a processor configured to identify qualities of the plurality of images, process the plurality of images using at least one artificial intelligence model corresponding to the identified qualities, and obtain a graphic image including the processed plurality of images, and the at least one artificial intelligence model is trained to increase a quality of an input image.
Abstract:
A method of operating a memory controller, the method including performing a state shaping operation on received data based on state shaping information in response to a write request, the received data and the write request being received from a host, the state shaping information representing a memory cell characteristic corresponding to a memory cell group on which the received data is to be programmed, and the state shaping information being received from a memory device, and transmitting transformation data to the memory device, the transformation data being generated through the state shaping operation.
Abstract:
Disclosed are a display apparatus, an image providing apparatus, and methods of controlling the same, the display apparatus including: a display; and a processor configured to: decode an encoded video stream, decompress the video stream through a neural network including a plurality of channels and a plurality of layers with a parameter set based on learning, and perform image compensation determined based on learning about the decompression with respect to the video stream.
Abstract:
Disclosed are a display apparatus and a method of controlling the same, the display apparatus including: a video decoder configured to decode a video signal; and an artificial intelligence (AI) scaler including a plurality of filters provided to make an output of a certain filter be used as an input of another filter, and configured to control a resolution of an image by processing the decoded video signal, each of the plurality of filters being selectively turned on or off based on a control signal, the filter being turned on processing the video signal based on a parameter set by learning, and the filter being turned off bypassing and outputting the input video signal.
Abstract:
A memory device for improving the speed of a program operation and an operating method thereof is provided. The memory device includes a memory cell array including a plurality of memory cells, a voltage generator configured to generate voltages for one or more program operations and a verify operation performed on the plurality of memory cells, a control logic configured to perform a control operation on the plurality of memory cells so that a first program and a second program loop are performed, a second program operation being performed based on a compensation voltage level determined based on a result of the first verify operation, and a plurality of bit lines connected to the memory cell array, wherein the first verify operation includes first even sensing and second even sensing on even-numbered bit lines, and first odd sensing and second odd sensing on odd-numbered bit lines.
Abstract:
An electronic apparatus includes a memory configured to store a plurality of images; and a processor configured to identify qualities of the plurality of images, process the plurality of images using at least one artificial intelligence model corresponding to the identified qualities, and obtain a graphic image including the processed plurality of images, and the at least one artificial intelligence model is trained to increase a quality of an input image.
Abstract:
A memory device for improving the speed of a program operation and an operating method thereof is provided. The memory device includes a memory cell array including a plurality of memory cells, a voltage generator configured to generate voltages for one or more program operations and a verify operation performed on the plurality of memory cells, a control logic configured to perform a control operation on the plurality of memory cells so that a first program and a second program loop are performed, a second program operation being performed based on a compensation voltage level determined based on a result of the first verify operation, and a plurality of bit lines connected to the memory cell array, wherein the first verify operation includes first even sensing and second even sensing on even-numbered bit lines, and first odd sensing and second odd sensing on odd-numbered bit lines.
Abstract:
Disclosed are a display apparatus and a method of controlling the same, the display apparatus including: a video decoder configured to decode a video signal; and an artificial intelligence (AI) scaler including a plurality of filters provided to make an output of a certain filter be used as an input of another filter, and configured to control a resolution of an image by processing the decoded video signal, each of the plurality of filters being selectively turned on or off based on a control signal, the filter being turned on processing the video signal based on a parameter set by learning, and the filter being turned off bypassing and outputting the input video signal.
Abstract:
A nonvolatile memory device may include a memory cell array which is arranged in rows and columns and has multi-level memory cells; a voltage generator providing a plurality of read voltages to a selected row of the memory cell array; and control logic performing a plurality of page read operations using the read voltages. A first read voltage and a second read voltage among the plurality of read voltages are each associated with a higher probability of occurrence of a bit read error than at least one other read voltage among the plurality of read voltages. The control logic uses the first read voltage and the second read voltage in different page read operations than each other.