SEMICONDUCTOR DEVICE
    11.
    发明公开

    公开(公告)号:US20240074193A1

    公开(公告)日:2024-02-29

    申请号:US18210729

    申请日:2023-06-16

    CPC classification number: H10B43/27 H10B43/35 H10B43/40

    Abstract: A semiconductor device includes a lower circuit pattern on a substrate, a common source plate (CSP) on the lower circuit pattern, a gate electrode structure including gate electrodes spaced apart from each other on the CSP in a first direction that is substantially perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction that is substantially parallel to the upper surface of the substrate, a first insulation pattern structure on a portion of the CSP that is adjacent to the gate electrode structure in the second direction, and a first division pattern extending on the CSP in a third direction that is substantially parallel to the upper surface of the substrate and that crosses the second direction, the first division pattern extending through a portion of the gate electrode structure that is adjacent to the first insulation pattern structure.

    Display apparatus and method of controlling the same

    公开(公告)号:US11265564B2

    公开(公告)日:2022-03-01

    申请号:US16680974

    申请日:2019-11-12

    Abstract: Disclosed are a display apparatus and a method of controlling the same, the display apparatus including: a video decoder configured to decode a video signal; and an artificial intelligence (AI) scaler including a plurality of filters provided to make an output of a certain filter be used as an input of another filter, and configured to control a resolution of an image by processing the decoded video signal, each of the plurality of filters being selectively turned on or off based on a control signal, the filter being turned on processing the video signal based on a parameter set by learning, and the filter being turned off bypassing and outputting the input video signal.

    Memory device for improving speed of program operation and operating method thereof

    公开(公告)号:US11972111B2

    公开(公告)日:2024-04-30

    申请号:US18052350

    申请日:2022-11-03

    CPC classification number: G06F3/0613 G06F3/0629 G06F3/0679

    Abstract: A memory device for improving the speed of a program operation and an operating method thereof is provided. The memory device includes a memory cell array including a plurality of memory cells, a voltage generator configured to generate voltages for one or more program operations and a verify operation performed on the plurality of memory cells, a control logic configured to perform a control operation on the plurality of memory cells so that a first program and a second program loop are performed, a second program operation being performed based on a compensation voltage level determined based on a result of the first verify operation, and a plurality of bit lines connected to the memory cell array, wherein the first verify operation includes first even sensing and second even sensing on even-numbered bit lines, and first odd sensing and second odd sensing on odd-numbered bit lines.

    MEMORY DEVICE FOR IMPROVING SPEED OF PROGRAM OPERATION AND OPERATING METHOD THEREOF

    公开(公告)号:US20230146741A1

    公开(公告)日:2023-05-11

    申请号:US18052350

    申请日:2022-11-03

    CPC classification number: G06F3/0613 G06F3/0629 G06F3/0679

    Abstract: A memory device for improving the speed of a program operation and an operating method thereof is provided. The memory device includes a memory cell array including a plurality of memory cells, a voltage generator configured to generate voltages for one or more program operations and a verify operation performed on the plurality of memory cells, a control logic configured to perform a control operation on the plurality of memory cells so that a first program and a second program loop are performed, a second program operation being performed based on a compensation voltage level determined based on a result of the first verify operation, and a plurality of bit lines connected to the memory cell array, wherein the first verify operation includes first even sensing and second even sensing on even-numbered bit lines, and first odd sensing and second odd sensing on odd-numbered bit lines.

    DISPLAY APPARATUS AND METHOD OF CONTROLLING THE SAME

    公开(公告)号:US20200154123A1

    公开(公告)日:2020-05-14

    申请号:US16680974

    申请日:2019-11-12

    Abstract: Disclosed are a display apparatus and a method of controlling the same, the display apparatus including: a video decoder configured to decode a video signal; and an artificial intelligence (AI) scaler including a plurality of filters provided to make an output of a certain filter be used as an input of another filter, and configured to control a resolution of an image by processing the decoded video signal, each of the plurality of filters being selectively turned on or off based on a control signal, the filter being turned on processing the video signal based on a parameter set by learning, and the filter being turned off bypassing and outputting the input video signal.

    Nonvolatile memory device and memory system including the same
    20.
    发明授权
    Nonvolatile memory device and memory system including the same 有权
    非易失性存储器件和包括其的存储器系统

    公开(公告)号:US09251904B2

    公开(公告)日:2016-02-02

    申请号:US14458567

    申请日:2014-08-13

    Abstract: A nonvolatile memory device may include a memory cell array which is arranged in rows and columns and has multi-level memory cells; a voltage generator providing a plurality of read voltages to a selected row of the memory cell array; and control logic performing a plurality of page read operations using the read voltages. A first read voltage and a second read voltage among the plurality of read voltages are each associated with a higher probability of occurrence of a bit read error than at least one other read voltage among the plurality of read voltages. The control logic uses the first read voltage and the second read voltage in different page read operations than each other.

    Abstract translation: 非易失性存储器件可以包括以行和列布置并具有多级存储单元的存储单元阵列; 电压发生器,向存储单元阵列的选定行提供多个读取电压; 以及控制逻辑,使用读取的电压执行多个页面读取操作。 多个读取电压之间的第一读取电压和第二读取电压各自与多个读取电压中的至少一个其他读取电压的比特读取错误的发生概率相关。 控制逻辑在彼此不同的页读操作中使用第一读电压和第二读电压。

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