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    Training method of memory device and electronic device and electronic system including the same
    13.
    发明授权
    Training method of memory device and electronic device and electronic system including the same 有权

    公开(公告)号：US11461113B2

    公开(公告)日：2022-10-04

    申请号：US16906023

    申请日：2020-06-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jang Seon Park ,  Jong Un Kim ,  Ju Chan Lee ,  Hyung Lae Eun ,  Dong Kim ,  In Hoon Park

    IPC: G06F9/445 ,  G06F12/02 ,  G06N5/02 ,  G06F1/20 ,  G06N20/00 ,  G06F1/3296

    Abstract: An electronic device includes: a memory device; a nonvolatile memory configured to store a plurality of first configuration parameters respectively corresponding to operating voltages of the memory device and a plurality of second configuration parameters respectively corresponding to operating temperatures of the memory device; and a memory controller configured to: determine a value of a third configuration parameter corresponding to an operating voltage of the memory device among the plurality of first configuration parameters stored in the nonvolatile memory without performing a training operation, determine a value of a fourth configuration parameter corresponding to an operating temperature of the memory device among the plurality of second configuration parameters stored in the nonvolatile memory without performing the training operation, and drive the memory device according to the determined values of the third and the fourth configuration parameters.

    Method of controlling repair of volatile memory device and storage device performing the same
    15.
    发明授权
    Method of controlling repair of volatile memory device and storage device performing the same 有权

    公开(公告)号：US11301317B2

    公开(公告)日：2022-04-12

    申请号：US16790256

    申请日：2020-02-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong Kim ,  Inhoon Park ,  Jangseon Park ,  Hyunglae Eun

    IPC: G06F11/07 ,  G06F11/10

    Abstract: A method of controlling repair of a volatile memory device, includes, performing a patrol read operation repeatedly to provide error position information of errors included in read data from a volatile memory device, generating accumulated error information by accumulating the error position information based on the patrol read operation performed repeatedly, determining error attribute based on the accumulated error information, the error attribute indicating correlation between the errors and a structure of the volatile memory device, and performing a runtime repair operation with respect to the volatile memory device based on the accumulated error information and the error attribute. The errors may be managed efficiently to prevent failure of the volatile memory device, and thus performance and lifetime of the volatile memory device and the storage device may be enhanced.

    Semiconductor memory devices, memory systems and methods of controlling of repair of semiconductor memory devices
    16.
    发明授权
    Semiconductor memory devices, memory systems and methods of controlling of repair of semiconductor memory devices 有权

    公开(公告)号：US11163640B2

    公开(公告)日：2021-11-02

    申请号：US16824660

    申请日：2020-03-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunglae Eun ,  Dong Kim ,  Inhoon Park

    IPC: G06F11/10 ,  G11C29/44 ,  G11C11/4093 ,  G11C11/408

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit connected between the memory cell array and the ECC engine, an error information register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The control logic circuit controls the ECC engine, the I/O gating circuit and the error information register based on a command and address. The I/O gating circuit provides the ECC engine with codewords which are read from the memory cell array through refresh operations on the plurality of memory cell rows. The ECC engine performs an ECC decoding on main data of the codewords based on parity bits of the codewords and provides error generation signals to the control logic circuit in response to detecting correctable errors with respect to a corresponding address resulting from performing the ECC decoding.

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