Abstract:
A controller for a display panel includes a detector, a timing controller, and a voltage generator. The detector detects a predetermined pattern in an image signal. The timing controller generates a control signal based on detection of the pattern. The voltage generator changes at least one driving voltage for a display panel from a first level to a second level based on the control signal. The predetermined pattern may correspond to at least one region having a predetermined arrangement of at least first and second gray scale values of pixels in an image corresponding to the image signal.
Abstract:
A display driving circuit includes a digital-to-analog converter configured to convert a digital image signal to an analog image signal, and a buffer circuit configured to receive the analog image signal and to output an output signal to be applied to a data line, where the buffer circuit includes an input stage configured to receive the analog image signal and to output a first signal, a first output stage configured to receive a first voltage and a second voltage and to output the output signal, a second output stage configured to receive a third voltage and a fourth voltage and to output the output signal, and a selection circuit configured to apply the first signal from the input stage to the first output stage or the second output stage in response to a mode signal.
Abstract:
A display device includes: a display panel in which pixels are arranged; a first circuit board configured to provide a first driving signal to the display panel; and a second circuit board connecting the display panel and the first circuit board and having a first region in which a driving chip providing a second driving signal to the display panel is arranged and a second region surrounding the first region, the first region and the second region being defined in the second circuit board, wherein: the second circuit board comprises a first line electrically connected to the driving chip and a second line electrically insulated from the driving chip; the second line comprises a common line in the first region; and the width of the common line decreases as the common line becomes farther away from the first circuit board on a plane.
Abstract:
A display device includes: a display panel including first pads arranged along a first direction, and second pads spaced apart from the first pads; a first connection circuit board electrically connected to the first pads; and a second connection circuit board electrically connected to the second pads. The first connection circuit board includes: first output pads electrically connected to the first pads; and at least two first protrusion parts spaced along the first direction and protruding in a second direction crossing the first direction. The second connection circuit board includes: second output pads electrically connected to the second pads; and at least one second protrusion part protruding in the second direction, and located between the first protrusion parts when viewed on a plane that is parallel to a surface of the display panel.
Abstract:
A method of operating a display device involves detecting whether a frame mode of the display device is a normal mode in which image data are received with a constant frame rate or a variable frame mode in which the image data are received with a variable frame rate. An output buffer drivability of a data driver included in the display device may be set according to the detected frame mode, and an image is displayed by outputting data voltages corresponding to the image data with slew rates corresponding to the set output buffer drivability. Power consumption in output buffer amplifiers may be selectively lowered by setting a relatively low output buffer drivability corresponding to a relatively low slew rate.
Abstract:
A liquid crystal display device, including: pixels; data lines and scan lines coupled to the pixels; and a driver configured to supply a scan signal to the scan lines, and supply a data voltage to the data lines. The data lines include first to third data lines, to which a data voltage having a positive polarity is supplied, and which are adjacent to each other, and fourth to sixth data lines, to which a data voltage having a negative polarity is supplied, and which are adjacent to each other.
Abstract:
A driving circuit includes a receiver configured to receive an image control signal comprising a data signal and a clock signal, separate the data signal from the clock signal and output the separated data and clock signals, a clock recovery unit generating a reference clock signal based on the clock signal and generating a plurality of multi-phase clock signals having different phases from that of the reference clock signal, an output clock generation unit outputting an output clock signal in synchronization with the clock signal and the plurality of multi-phase clock signals, and a data output unit driving a plurality of data lines with a data driving signal corresponding to the data signal in synchronization with the output clock signal, and the output clock generation unit outputs the plurality of multi-phase clock signals.