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公开(公告)号：US11609623B2
公开(公告)日：2023-03-21
申请号：US16119929
申请日：2018-08-31
Applicant: QUALCOMM Incorporated
IPC: G06F1/32 , G06F1/3287 , G06F1/3234 , G06F1/3296 , G06N3/063 , G06N3/04
Abstract: A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also includes multiple cores defined on each tier and coupled to the power manager. Each core includes at least a processing element, a non-volatile memory, and a communications module.
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12.发明授权公开(公告)号：US09712168B1
公开(公告)日：2017-07-18
申请号：US15264983
申请日：2016-09-14
Applicant: QUALCOMM Incorporated
Inventor： Giby Samson , Yu Pu , Yang Du
IPC: H03B1/00 , H03K3/00 , H03K19/003 , H03K3/03 , G06F17/50
CPC classification number: H03K19/00369 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/32145 , H01L2224/48145 , H01L2224/73207 , H01L2224/73265 , H03K3/0315
Abstract: Systems and methods for process variation power control in three-dimensional integrated circuits (3DICs) are disclosed. In an exemplary aspect, at least one process variation sensor is placed in each tier of a 3DIC. The process variation sensors report information related to a speed characteristic for elements within the respective tier to a decision logic. The decision logic is programmed to weight output from the process variation sensors according to relative importance of logic path segments in the respective tiers. The weighted outputs are combined to generate a power control signal that is sent to a power management unit (PMU). By weighting the importance of the logic path segments, a compromise voltage may be generated by the PMU which is “good enough” for all the elements in the various tiers to provide acceptable performance.
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公开(公告)号：US20160267214A1
公开(公告)日：2016-09-15
申请号：US14643096
申请日：2015-03-10
Applicant: QUALCOMM Incorporated
Inventor： Sung Kyu Lim , Francois Ibrahim Atallah , Rashid Ahmed Akbar Attar , Keith Alan Bowman , Yang Du , Juzer Zainuddin Fatehi , Jai Ganesh Kumar , Yu Pu , Giby Samson , Kendrick Hoy Leong Yuen
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5031 , G06F17/5036 , G06F2217/62 , G06F2217/84
Abstract: Clock tree design methods for ultra-wide voltage range circuits are disclosed. In one aspect, place and route software creates an integrated circuit (IC) in an optimal configuration at a first voltage condition. A first clock tree is created as part of the place and route process. Clock skew for the first clock tree is evaluated and minimized through insertion of bypassable delay elements. The delay elements are then removed from the wiring routing diagram. A second voltage condition is identified, and clock tree generation software is allowed to optimize the wiring routing diagram for the second voltage condition. The second clock tree generation software may insert more bypassable delay elements into the wiring routing diagram that allow clock skew optimization at the second voltage condition. The initial bypassable delay elements are then reinserted into the wiring routing diagram and a finished IC is established.
Abstract translation: 公开了用于超宽电压范围电路的时钟树设计方法。 在一个方面，放置和路由软件在第一电压条件下以最佳配置创建集成电路（IC）。 第一个时钟树是作为地点和路由过程的一部分而创建的。 通过插入可旁路延迟元件来评估和最小化第一个时钟树的时钟偏移。 然后将延迟元件从布线图中删除。 识别出第二电压条件，并允许时钟树生成软件优化第二电压条件的布线布线图。 第二个时钟树生成软件可以在布线布线图中插入更多的可旁路延迟元件，允许在第二电压条件下进行时钟偏移优化。 然后将初始可旁路延迟元件重新插入到布线布线图中，并建立成品IC。
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公开(公告)号：US10191106B2
公开(公告)日：2019-01-29
申请号：US15015547
申请日：2016-02-04
Applicant: QUALCOMM Incorporated
Inventor： Yu Pu , Giby Samson , Kendrick Hoy Leong Yuen
Abstract: Methods and apparatus for identifying a process corner are provided. Provided is an exemplary method for identifying a process corner of an integrated circuit (IC). The IC has a first asymmetrical ring oscillator (ARO1) including pull-up transistors that have a low threshold voltage (LVT) and pull-down transistors that have a regular threshold voltage (RVT), and has a second asymmetrical ring oscillator (ARO2) including pull-up transistors that have an RVT and pull-down transistors having an LVT. The exemplary method includes applying an ultra-low power supply voltage to the ARO1 and the ARO2 that causes the integrated circuit to operate near a verge of malfunction, measuring an output frequency of the ARO1, measuring an output frequency of the ARO2, calculating a calculated ratio of the output frequency of the ARO1 and the output frequency of the ARO2, and comparing the calculated ratio to a fiduciary ratio to identify the process corner.
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公开(公告)号：US20180041210A1
公开(公告)日：2018-02-08
申请号：US15230885
申请日：2016-08-08
Applicant: QUALCOMM Incorporated
Inventor： Yu Pu , Giby Samson
CPC classification number: H03K19/0019 , H02J7/025 , H02J50/10 , H03K19/01707
Abstract: Electronic devices employing adiabatic logic circuits with wireless charging are disclosed. In one aspect, an electronic device is provided. The electronic device includes a power circuit employing an alternating current (AC) coupler circuit configured to receive a wireless AC signal and generate a wired AC signal based on the wireless AC signal. The power circuit includes a power output configured to provide an AC power signal based on the wired AC signal generated by the AC coupler circuit. The AC power signal is generated based on the wireless charging capability of the AC coupler circuit. The electronic device employs a digital logic system that includes a power rail electrically coupled to an adiabatic logic circuit. The AC power signal is provided to the power rail to provide power to the adiabatic logic circuit. Wirelessly charging the adiabatic logic circuit consumes less power than conventional non-wireless charging circuitry.
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Patent Agency Ranking
公开(公告)号：US10552563B2
公开(公告)日：2020-02-04
申请号：US15866876
申请日：2018-01-10
Applicant: QUALCOMM Incorporated
Inventor： Mark Lin , Yu Pu , Giby Samson
Abstract: Aspects of the disclosure are directed to a digital design with bundled data asynchronous logic and body-biasing tuning. In one aspect, implementation includes establishing a control path between a first controller and a second controller using a handshaking protocol; establishing a data path between a first latch and a second latch using a bundled data technique; executing a first dynamic body biasing tuning by applying a first body bias signal to the control path; executing a second dynamic body biasing tuning by applying a second body bias signal to the data path. The digital design includes a first controller with a control path to connect to a second controller, wherein a first body bias tuning signal tunes body bias in the control path, a first latch with a data path to connect to a second latch, wherein a second body bias tuning signal tunes body bias in the data path.
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公开(公告)号：US10432197B2
公开(公告)日：2019-10-01
申请号：US15230885
申请日：2016-08-08
Applicant: QUALCOMM Incorporated
Inventor： Yu Pu , Giby Samson
IPC: H03K19/00 , H02J7/02 , H02J50/10 , H03K19/017
Abstract: Electronic devices employing adiabatic logic circuits with wireless charging are disclosed. In one aspect, an electronic device is provided. The electronic device includes a power circuit employing an alternating current (AC) coupler circuit configured to receive a wireless AC signal and generate a wired AC signal based on the wireless AC signal. The power circuit includes a power output configured to provide an AC power signal based on the wired AC signal generated by the AC coupler circuit. The AC power signal is generated based on the wireless charging capability of the AC coupler circuit. The electronic device employs a digital logic system that includes a power rail electrically coupled to an adiabatic logic circuit. The AC power signal is provided to the power rail to provide power to the adiabatic logic circuit. Wirelessly charging the adiabatic logic circuit consumes less power than conventional non-wireless charging circuitry.
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公开(公告)号：US10394471B2
公开(公告)日：2019-08-27
申请号：US15245725
申请日：2016-08-24
Applicant: QUALCOMM Incorporated
Inventor： Giby Samson , Keith Alan Bowman , Yu Pu , Francois Ibrahim Atallah
Abstract: Adaptive power regulation methods and systems are disclosed. In one aspect, one or more process sensors for memory elements are provided, which report information relating to inherent speed characteristics of sub-elements within the memory elements. Based on this reported information, a controller ascertains an appropriate power level to insure a proper data retention voltage (DRV) is applied on voltage rails by a power management unit (PMU) circuit. By using the proper DRV based on the speed characteristics of the sub-elements within the memory elements, power conservation is achieved.
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公开(公告)号：US20190213296A1
公开(公告)日：2019-07-11
申请号：US15866876
申请日：2018-01-10
Applicant: QUALCOMM Incorporated
Inventor： Mark Lin , Yu Pu , Giby Samson
IPC: G06F17/50
Abstract: Aspects of the disclosure are directed to a digital design with bundled data asynchronous logic and body-biasing tuning. In one aspect, implementation includes establishing a control path between a first controller and a second controller using a handshaking protocol; establishing a data path between a first latch and a second latch using a bundled data technique; executing a first dynamic body biasing tuning by applying a first body bias signal to the control path; executing a second dynamic body biasing tuning by applying a second body bias signal to the data path. The digital design includes a first controller with a control path to connect to a second controller, wherein a first body bias tuning signal tunes body bias in the control path, a first latch with a data path to connect to a second latch, wherein a second body bias tuning signal tunes body bias in the data path.
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公开(公告)号：US10050610B2
公开(公告)日：2018-08-14
申请号：US14642859
申请日：2015-03-10
Applicant: QUALCOMM Incorporated
Inventor： Giby Samson , Yu Pu , Kendrick Hoy Leong Yuen
Abstract: Clock distribution schemes with wide operating voltage ranges are disclosed. In one aspect, an operating voltage level or condition within a computing device is sensed. In a first voltage condition, delay elements are used within a clock tree to minimize clock skew. In a second voltage condition, one or more delay and/or clocked elements are bypassed to minimize clock skew at the second voltage condition. In addition to controlling clock skew, power may be conserved by depowering the bypassed elements. Controlling clock skew in this fashion improves operation of a computing device that includes the clock tree and may improve battery life.
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