公开(公告)号：US10963035B2

公开(公告)日：2021-03-30

申请号：US16155824

申请日：2018-10-09

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  James Lionel Panian ,  Richard Dominic Wietfeldt ,  Mohit Kishore Prasad ,  Amit Gil ,  Shaul Yohai Yifrach

IPC: G06F1/3234 ,  G06F13/40 ,  G06F13/10 ,  G06F1/3206

Abstract: A system for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems, while maintaining both lower level physical layer (PHY) pin requirements and upper layer functionality being capable of both differential and single-ended signaling modes optimized for power savings. An apparatus includes an integrated circuit (IC) adapted to be connected to a Peripheral Component Interconnect (PCI) Express (PCIe) bus. The IC includes a control block selects between differential and single-ended signaling for the PCIe bus. The single-ended signaling is transmitted through existing pins of the IC that are coupled to the PCIe bus for differential signaling when single-ended signaling is selected for the PCIe bus.

公开(公告)号：US10795400B2

公开(公告)日：2020-10-06

申请号：US15966077

申请日：2018-04-30

Applicant: QUALCOMM Incorporated

Inventor： Yiftach Benjamini ,  Amit Gil ,  Shaul Yohai Yifrach

IPC: G06F1/12 ,  G06F13/42

Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.

公开(公告)号：US10310585B2

公开(公告)日：2019-06-04

申请号：US15726566

申请日：2017-10-06

Applicant: QUALCOMM Incorporated

Inventor： Shaul Yohai Yifrach ,  Amit Gil ,  James Lionel Panian ,  Ofer Rosenberg ,  Richard Dominic Wietfeldt

IPC: G06F1/32 ,  G06F13/42 ,  G06F1/3234 ,  G06F13/40 ,  H01L23/29 ,  H04L12/931

Abstract: A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.

公开(公告)号：US20190058780A1

公开(公告)日：2019-02-21

申请号：US15678531

申请日：2017-08-16

Applicant: QUALCOMM Incorporated

Inventor： Amit Gil ,  Shaul Yohai Yifrach

IPC: H04L29/06 ,  G06F13/12 ,  H04L12/807 ,  H04L12/801

Abstract: Alternate acknowledgment (ACK) signals in a coalescing Transmission Control Protocol/Internet Protocol (TCP/IP) system are disclosed. In one aspect, a network interface card (NIC) examines packet payloads, and the NIC generates an ACK signal for a sending server before sending a coalesced packet to an internal processor. Further, the NIC may examine incoming packets and send an ACK signal to the internal processor for ACK signals that are received from the sending server before sending the coalesced packet to the internal processor. By extracting and sending the ACK signals before sending the corresponding payloads in the coalesced packet, latency that would otherwise be incurred waiting for the ACK signal is eliminated. Elimination of such latency may improve network performance and may provide power savings.

公开(公告)号：US20180120921A1

公开(公告)日：2018-05-03

申请号：US15726566

申请日：2017-10-06

Applicant: QUALCOMM Incorporated

Inventor： Shaul Yohai Yifrach ,  Amit Gil ,  James Lionel Panian ,  Ofer Rosenberg ,  Richard Dominic Wietfeldt

IPC: G06F1/32 ,  G06F13/40 ,  H04L12/931 ,  H01L23/29

CPC classification number: G06F1/3253 ,  G06F13/4072 ,  G06F13/4273 ,  G06F13/4291 ,  H01L23/291 ,  H04L49/40 ,  Y02D10/151

Abstract: A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.

公开(公告)号：US20180041614A1

公开(公告)日：2018-02-08

申请号：US15226429

申请日：2016-08-02

Applicant: QUALCOMM Incorporated

Inventor： Tomer Rafael Ben-Chen ,  Amit Gil ,  Dan Gilboa Waizman ,  Deepak Jindal ,  Ayala Miller ,  Shaul Yohai Yifrach

IPC: H04L29/06 ,  H04L12/741

CPC classification number: H04L69/22 ,  H04L45/741 ,  H04L45/745 ,  H04L69/04 ,  H04L69/08 ,  H04L69/18 ,  H04L69/321

Abstract: Hardware-based packet processing circuitry is provided. In this regard, hardware-based packet processing circuitry includes header processing circuitry and payload processing circuitry. The hardware-based packet processing circuitry receives a header portion and a payload portion of an incoming packet in a first packet format. The header processing circuitry and the payload processing circuitry process the header portion and the payload portion to form a processed header portion and a processed payload portion, respectively. The hardware-based packet processing circuitry generates an outgoing packet in a second packet format based on the processed header portion and the processed payload portion. By processing the incoming packet separately in the header processing circuitry and the payload processing circuitry, it is possible to accelerate selected steps (e.g., ciphering/deciphering, compression/de-compression, checksum, etc.) of packet processing via dedicated hardware functional block(s), thus reducing computing resource requirement and overhead associated with software-based packet processing.

公开(公告)号：US20160337257A1

公开(公告)日：2016-11-17

申请号：US14713028

申请日：2015-05-15

Applicant: QUALCOMM Incorporated

Inventor： Shaul Yohai Yifrach ,  Amit Gil

IPC: H04L12/863

CPC classification number: H04L47/6205 ,  H04L47/623 ,  H04L49/3027

Abstract: Aspects disclosed in the detailed description include head-of-line blocking (HOLB) mitigation in communication devices. Output queues employed by a communication device for transmitting data are susceptible to HOLB. In this regard, in one aspect, a queue monitoring logic is configured to detect HOLB by measuring and comparing a depth(s) of an output queue(s) against a queue-overflow threshold. If the depth(s) of the output queue(s) exceeds the queue-overflow threshold, a queue weight(s) of a corresponding input queue(s) is decreased to reduce data flow into the output queue(s), thus mitigating the HOLB in the output queue(s). In another aspect, the queue monitoring logic is configured to detect queue depletion by comparing the depth(s) of the output queue(s) against a queue-depletion threshold. By mitigating the HOLB and the data starvation in the output queue(s), it is possible to optimize the output queue(s) to achieve higher throughput and data integrity with lower power consumption.

Abstract translation: 在详细描述中公开的方面包括通信设备中的行前阻止（HOLB）抑制。 用于传输数据的通信设备使用的输出队列易受HOLB的影响。 在这方面，在一方面，队列监视逻辑被配置为通过测量和比较输出队列的深度与队列溢出阈值来检测HOLB。 如果输出队列的深度超过队列溢出阈值，则减少对应输入队列的队列权重以减少进入输出队列的数据流，从而减轻 输出队列中的HOLB。 在另一方面，队列监视逻辑被配置为通过将输出队列的深度与队列耗尽阈值进行比较来检测队列耗尽。 通过减轻输出队列中的HOLB和数据不足，可以优化输出队列，以便以更低的功耗实现更高的吞吐量和数据完整性。

公开(公告)号：US20200341506A1

公开(公告)日：2020-10-29

申请号：US16927657

申请日：2020-07-13

Applicant: QUALCOMM Incorporated

Inventor： Yiftach Benjamini ,  Amit Gil ,  Shaul Yohai Yifrach

IPC: G06F1/12 ,  G06F13/42

Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.

公开(公告)号：US20190332137A1

公开(公告)日：2019-10-31

申请号：US15966077

申请日：2018-04-30

Applicant: QUALCOMM Incorporated

Inventor： Yiftach Benjamini ,  Amit Gil ,  Shaul Yohai Yifrach

IPC: G06F1/12 ,  G06F13/42 ,  G06F13/362 ,  G06F1/10

Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.

公开(公告)号：US20190250876A1

公开(公告)日：2019-08-15

申请号：US16260299

申请日：2019-01-29

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Sharon Graif ,  Shaul Yohai Yifrach

IPC: G06F3/16

CPC classification number: G06F3/162 ,  G06F2213/0002 ,  G06F2213/0026

Abstract: Systems and methods for providing split read transactions over an audio communication bus are disclosed. In one aspect, a device that receives a read command informs a requester that data is not yet available and to try again at a future time, potentially outside the traditional response window. In the meantime, the receiving device begins fetching the requested data to have available when the requester makes a subsequent request. By providing a not yet response, data may be fetched from a memory element in a low-power state after it has been taken out of the low-power state or data may be fetched from a remote location or over a slow internal bus.