公开(公告)号：US20150294697A1

公开(公告)日：2015-10-15

申请号：US14251315

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Rui Li ,  David Li ,  Tahseen Shakir ,  Sei Seung Yoon

IPC: G11C7/06 ,  G11C11/419

CPC classification number: G11C7/065 ,  G11C11/419

Abstract: A sense amplifier is provided that includes a skewed latch that latches a voltage difference developed responsive to a read operation on an accessed memory cell. The skewed latch includes a loaded logic gate that is cross-coupled with an unloaded logic gate. The loaded logic gate drives the unloaded logic gate and an output transistor whereas the unloaded logic gate drives only the loaded logic gate.

Abstract translation: 提供了一种读出放大器，其包括倾斜的锁存器，其锁存响应于对所访问的存储器单元的读取操作产生的电压差。 偏斜锁存器包括与卸载逻辑门交叉耦合的加载逻辑门。 加载的逻辑门驱动无载逻辑门和输出晶体管，而无负载逻辑门仅驱动加载的逻辑门。

公开(公告)号：US11810636B2

公开(公告)日：2023-11-07

申请号：US17574431

申请日：2022-01-12

Applicant: QUALCOMM Incorporated

Inventor： Rui Li ,  De Lu ,  Venkat Narayanan

IPC: G11C7/10

CPC classification number: G11C7/1009 ,  G11C7/1087

Abstract: An aspect of the disclosure relates to a latch array, including: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs coupled to a set of bitlines, respectively; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write-bit inputs configured to receive a set of write-bit signals, and a set of write-bit outputs coupled to a set of write-bit lines, respectively; and an array of slave latches, wherein the slave latches in columns of the array include a second set of data inputs coupled to the set of bitlines, and a second set of write-bit inputs coupled to the set of write-bit lines, respectively.

公开(公告)号：US09318165B2

公开(公告)日：2016-04-19

申请号：US14218691

申请日：2014-03-18

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Rui Li ,  Sei Seung Yoon ,  Gregory Ameriada Uvieghara

IPC: H03F3/45 ,  G11C7/06 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C7/062 ,  G11C17/16 ,  G11C17/18 ,  H03F3/45183 ,  H03F3/45497 ,  H03F2203/45402 ,  H03F2203/45604 ,  H03F2203/45641 ,  H03F2203/45652

Abstract: A sense amplifier is disclosed that includes an amplifier circuit configured to receive, at an input, an input signal including an input level, the amplifier circuit configured to provide an amplified output signal including a gain with respect to the input level; and a feedback circuit coupled to receive the amplified output signal from the amplifier circuit, the feedback circuit configured to provide, at the input of the amplifier circuit, an adjusted version of the amplified output signal including a modified output magnitude based on common mode feedback.

Abstract translation: 公开了一种读出放大器，其包括放大器电路，其被配置为在输入端接收包括输入电平的输入信号，放大器电路被配置为提供包括相对于输入电平的增益的放大输出信号; 以及反馈电路，其耦合以从放大器电路接收放大的输出信号，所述反馈电路被配置为在放大器电路的输入处提供包括基于共模反馈的修改的输出幅度的经放大的输出信号的调整版本。