公开(公告)号：US10712807B2

公开(公告)日：2020-07-14

申请号：US15942207

申请日：2018-03-30

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Rajeev Jain ,  Byron Glenn Murphy ,  Lipeng Cao

IPC: G06F1/26 ,  G06F1/3287 ,  G06F1/3203

Abstract: Aspects of the disclosure are directed to saving always on (AON) routing of signals across chips, the disclosure includes turning ON a first power signal in a system on a chip (SOC) when a Power ON Reset (PoR) signal is asserted and a clamp control signal is asserted; turning ON a second power signal in the SOC after the first power signal is turned ON; de-asserting the PoR signal after the second power signal is turned ON; latching a logic signal with a LOW clamp keeper cell if the logic signal is at a LOW logic level or with a HIGH clamp keeper cell if the signal is at a HIGH logic level; and de-asserting the second power signal while a first section of the SOC routes the logic signal through a second section of the SOC.

公开(公告)号：US20190302876A1

公开(公告)日：2019-10-03

申请号：US15942207

申请日：2018-03-30

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Rajeev Jain ,  Byron Glenn Murphy ,  Lipeng Cao

IPC: G06F1/32

Abstract: Aspects of the disclosure are directed to saving always on (AON) routing of signals across chips, the disclosure includes turning ON a first power signal in a system on a chip (SOC) when a Power ON Reset (PoR) signal is asserted and a clamp control signal is asserted; turning ON a second power signal in the SOC after the first power signal is turned ON; de-asserting the PoR signal after the second power signal is turned ON; latching a logic signal with a LOW clamp keeper cell if the logic signal is at a LOW logic level or with a HIGH clamp keeper cell if the signal is at a HIGH logic level; and de-asserting the second power signal while a first section of the SOC routes the logic signal through a second section of the SOC.

公开(公告)号：US10317968B2

公开(公告)日：2019-06-11

申请号：US15471692

申请日：2017-03-28

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Rajeev Jain ,  Sassan Shahrokhinia ,  Lam Ho

IPC: G06F1/26 ,  H02J1/08 ,  H02J1/10

Abstract: An integrated circuit is disclosed for power multiplexing with an active load. In an example aspect, the integrated circuit includes a first power rail, a second power rail, a load power rail, multiple power-multiplexer tiles, and power-multiplexer control circuitry. The first power rail is at a first voltage, and the second power rail is at a second voltage. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and jointly perform a power-multiplexing operation responsive to a power-rail switching signal. Each power-multiplexer tile switches between coupling the load power rail to the first power rail and the second power rail. The power-multiplexer control circuitry is coupled to the first and second power rails and includes a comparator to produce a relative voltage signal based on the first and second voltages. The power-multiplexer control circuitry generates the power-rail switching signal based on the relative voltage signal.

公开(公告)号：US09990022B2

公开(公告)日：2018-06-05

申请号：US15199567

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Mong Chit Wong ,  Nam Dang ,  Rajeev Jain ,  Sassan Shahrokhinia ,  Yu Huang ,  Lipeng Cao

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/263 ,  H01L23/50 ,  H02J1/08 ,  H02J1/108 ,  H02J9/061

Abstract: An integrated circuit (IC) is disclosed herein for adaptive power multiplexing with a power distribution network. In an example aspect, the integrated circuit includes a first power rail, a second power rail, and a load power rail. The integrated circuit also includes multiple power-multiplexer tiles and power-multiplexer control circuitry. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and configured to jointly perform a power-multiplexing operation. Each power-multiplexer tile is configured to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The power-multiplexer control circuitry is configured to control a direction of current flow to prevent cross-conduction between the first power rail and the second power rail during the power-multiplexing operation.

公开(公告)号：US20160317122A1

公开(公告)日：2016-11-03

申请号：US15140001

申请日：2016-04-27

Applicant: QUALCOMM Incorporated

Inventor： Ricardo Paulo dos Santos Mendonca ,  Patrik Nils Lundqvist ,  Rashid Ahmed Akbar Attar ,  Rajeev Jain ,  Padmapriya Jagannathan

IPC: A61B8/00 ,  A61B8/08

CPC classification number: A61B8/4254 ,  A61B8/4245 ,  A61B8/4427 ,  A61B8/4444 ,  A61B8/4477 ,  A61B8/4483 ,  A61B8/467 ,  A61B8/483 ,  A61B8/5223 ,  A61B8/5238 ,  A61B8/5253 ,  A61B8/5269 ,  A61B8/5276 ,  A61B8/54 ,  A61B8/56 ,  A61B8/58 ,  G01C21/165 ,  G06F19/00

Abstract: An apparatus for noninvasive medical ultrasonography includes one or more ultrasonic transducers, one or more inertial sensors, one or more optical sensors, and a processor communicatively coupled with the ultrasonic transducers, the inertial sensors and the optical sensors. The processor is configured to estimate a position of the apparatus based on a combination of signals received from the ultrasonic transducers, the inertial sensors and the optical sensors.

Abstract translation: 用于非侵入性医学超声检查的装置包括一个或多个超声波换能器，一个或多个惯性传感器，一个或多个光学传感器，以及与超声换能器，惯性传感器和光学传感器通信耦合的处理器。 处理器被配置为基于从超声换能器，惯性传感器和光学传感器接收的信号的组合来估计装置的位置。