公开(公告)号：US10712807B2

公开(公告)日：2020-07-14

申请号：US15942207

申请日：2018-03-30

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Rajeev Jain ,  Byron Glenn Murphy ,  Lipeng Cao

IPC: G06F1/26 ,  G06F1/3287 ,  G06F1/3203

Abstract: Aspects of the disclosure are directed to saving always on (AON) routing of signals across chips, the disclosure includes turning ON a first power signal in a system on a chip (SOC) when a Power ON Reset (PoR) signal is asserted and a clamp control signal is asserted; turning ON a second power signal in the SOC after the first power signal is turned ON; de-asserting the PoR signal after the second power signal is turned ON; latching a logic signal with a LOW clamp keeper cell if the logic signal is at a LOW logic level or with a HIGH clamp keeper cell if the signal is at a HIGH logic level; and de-asserting the second power signal while a first section of the SOC routes the logic signal through a second section of the SOC.

公开(公告)号：US20190302876A1

公开(公告)日：2019-10-03

申请号：US15942207

申请日：2018-03-30

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Rajeev Jain ,  Byron Glenn Murphy ,  Lipeng Cao

IPC: G06F1/32

Abstract: Aspects of the disclosure are directed to saving always on (AON) routing of signals across chips, the disclosure includes turning ON a first power signal in a system on a chip (SOC) when a Power ON Reset (PoR) signal is asserted and a clamp control signal is asserted; turning ON a second power signal in the SOC after the first power signal is turned ON; de-asserting the PoR signal after the second power signal is turned ON; latching a logic signal with a LOW clamp keeper cell if the logic signal is at a LOW logic level or with a HIGH clamp keeper cell if the signal is at a HIGH logic level; and de-asserting the second power signal while a first section of the SOC routes the logic signal through a second section of the SOC.

公开(公告)号：US10317968B2

公开(公告)日：2019-06-11

申请号：US15471692

申请日：2017-03-28

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Rajeev Jain ,  Sassan Shahrokhinia ,  Lam Ho

IPC: G06F1/26 ,  H02J1/08 ,  H02J1/10

Abstract: An integrated circuit is disclosed for power multiplexing with an active load. In an example aspect, the integrated circuit includes a first power rail, a second power rail, a load power rail, multiple power-multiplexer tiles, and power-multiplexer control circuitry. The first power rail is at a first voltage, and the second power rail is at a second voltage. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and jointly perform a power-multiplexing operation responsive to a power-rail switching signal. Each power-multiplexer tile switches between coupling the load power rail to the first power rail and the second power rail. The power-multiplexer control circuitry is coupled to the first and second power rails and includes a comparator to produce a relative voltage signal based on the first and second voltages. The power-multiplexer control circuitry generates the power-rail switching signal based on the relative voltage signal.

公开(公告)号：US09665160B1

公开(公告)日：2017-05-30

申请号：US15156859

申请日：2016-05-17

Applicant: QUALCOMM Incorporated

Inventor： Lipeng Cao ,  Divjyot Bhan ,  Harshat Pant ,  Ramaprasath Vilangudipitchai

IPC: H03K3/356 ,  G06F1/32 ,  H03K3/3562 ,  H03K5/08 ,  G06F13/364

CPC classification number: G06F1/324 ,  G06F1/3287 ,  G06F13/364 ,  H03K3/0372 ,  H03K3/0375 ,  H03K3/3562 ,  H03K5/08 ,  Y02D10/171

Abstract: An integrated circuit (IC) is disclosed having a unified control scheme and a unifying architecture for different types of retention flip-flops (RFFs). In an example aspect, an IC includes a constant power rail to provide power during a power collapse period and a collapsible power rail to cease providing power during the power collapse period. The IC also includes a positive-edge-triggered (PET) RFF and a negative-edge-triggered (NET) RFF. The PET RFF includes a master portion and a slave portion, with the slave portion coupled to the constant power rail and the master portion coupled to the collapsible power rail. The NET RFF includes master and slave portions, with the master portion coupled to the constant power rail and the slave portion coupled to the collapsible power rail. In another example aspect, a control signal based on a clock and a retention signal may be routed to both RFFs.