公开(公告)号：US09733978B2

公开(公告)日：2017-08-15

申请号：US14837156

申请日：2015-08-27

Applicant: QUALCOMM Incorporated

Inventor： Dario Suarez Gracia ,  Tushar Kumar ,  Aravind Natarajan ,  Ravish Hastantram ,  Gheorghe Calin Cascaval ,  Han Zhao

IPC: G06F9/46 ,  G06F15/173 ,  G06F1/00 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0806 ,  G06F12/0862 ,  G06F12/12 ,  G06F11/34

CPC classification number: G06F9/48 ,  G06F9/4806 ,  G06F9/4831 ,  G06F9/4837 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/4893 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5022 ,  G06F9/5027 ,  G06F9/5033 ,  G06F9/5038 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5055 ,  G06F9/5083 ,  G06F9/5094 ,  G06F11/3419 ,  G06F11/3466 ,  G06F12/0806 ,  G06F12/0862 ,  G06F12/12 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/62 ,  Y02D10/22 ,  Y02D10/24

Abstract: Various embodiments include methods for data management in a computing device utilizing a plurality of processing units. Embodiment methods may include generating a data transfer heuristic model based on measurements from a plurality of sample data transfers between a plurality of data storage units. The generated data transfer heuristic model may be used to calculate data transfer costs for each of a plurality of tasks. The calculated data transfer costs may be used to schedule execution of the plurality of tasks in an execution order on selected ones of the plurality of processing units. The data transfer heuristic model may be updated based on measurements of data transfers occurring during the executions of the plurality of tasks (e.g., time, power consumption, etc.). Code executing on the processing units may indicate to a runtime when certain data blocks are no longer needed and thus may be evicted and/or pre-fetched for others.

公开(公告)号：US09632569B2

公开(公告)日：2017-04-25

申请号：US14451628

申请日：2014-08-05

Applicant: QUALCOMM Incorporated

Inventor： Dario Suarez Gracia ,  Han Zhao ,  Pablo Montesinos Ortego ,  Gheorghe Calin Cascaval ,  James Xenidis

IPC: G06F9/30 ,  G06F1/32 ,  G06F9/52 ,  G06F9/48

CPC classification number: G06F1/3296 ,  G06F9/4856 ,  G06F9/4893 ,  G06F9/526 ,  Y02D10/24

Abstract: Multi-processor computing device methods manage resource accesses by a signaling event manager signaling processor elements requesting access to a resource to wake up to access the resource when the resource is available or wait for an event when the resource is busy. Processor elements may enter a sleep state while awaiting access to the requested resource. When multiple elements are waiting for the resource, the processor element with a highest assigned priority is signaled to wake up when the resource is available without waking other elements. Priorities may be assigned to processor elements waiting for the resource based on a heuristic or parameter that may depend on a state of the computing device or the processor elements. A sleep duration may be estimated for a processor element waiting for a resource and the processor element may be removed from a scheduling queue or assigned another thread during the sleep duration.

公开(公告)号：US20170060633A1

公开(公告)日：2017-03-02

申请号：US14837156

申请日：2015-08-27

Applicant: QUALCOMM Incorporated

Inventor： Dario Suarez Gracia ,  Tushar Kumar ,  Aravind Natarajan ,  Ravish Hastantram ,  Gheorghe Calin Cascaval ,  Han Zhao

IPC: G06F9/50

CPC classification number: G06F9/48 ,  G06F9/4806 ,  G06F9/4831 ,  G06F9/4837 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/4893 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5022 ,  G06F9/5027 ,  G06F9/5033 ,  G06F9/5038 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5055 ,  G06F9/5083 ,  G06F9/5094 ,  G06F11/3419 ,  G06F11/3466 ,  G06F12/0806 ,  G06F12/0862 ,  G06F12/12 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/62 ,  Y02D10/22 ,  Y02D10/24

Abstract: Various embodiments include methods for data management in a computing device utilizing a plurality of processing units. Embodiment methods may include generating a data transfer heuristic model based on measurements from a plurality of sample data transfers between a plurality of data storage units. The generated data transfer heuristic model may be used to calculate data transfer costs for each of a plurality of tasks. The calculated data transfer costs may be used to schedule execution of the plurality of tasks in an execution order on selected ones of the plurality of processing units. The data transfer heuristic model may be updated based on measurements of data transfers occurring during the executions of the plurality of tasks (e.g., time, power consumption, etc.). Code executing on the processing units may indicate to a runtime when certain data blocks are no longer needed and thus may be evicted and/or pre-fetched for others.

Abstract translation: 各种实施例包括利用多个处理单元的计算设备中的数据管理方法。 实施方式可以包括基于来自多个数据存储单元之间的多个采样数据传输的测量来生成数据传输启发式模型。 生成的数据传输启发式模型可用于计算多个任务中的每一个的数据传输成本。 所计算的数据传输成本可以用于以多个处理单元中的选定的处理单元的执行顺序调度多个任务的执行。 可以基于在执行多个任务期间发生的数据传输的测量（例如，时间，功耗等）来更新数据传输启发式模型。 在处理单元上执行的代码可以向运行时指示某些数据块不再需要，并且因此可以被驱逐和/或预取其他数据块。

公开(公告)号：US20160292012A1

公开(公告)日：2016-10-06

申请号：US14673857

申请日：2015-03-30

Applicant: QUALCOMM Incorporated

Inventor： Behnam ROBATMILI ,  Shaizeen Dilawarhusen Aga ,  Dario Suarez Gracia ,  Arun Raman ,  Aravind Natarajan ,  Gheorghe Calin Cascaval ,  Pablo Montesinos Ortego ,  Han Zhao

IPC: G06F9/50

CPC classification number: G06F9/5066 ,  G06F9/5027

Abstract: Embodiments include computing devices, systems, and methods for task-based handling of repetitive processes in parallel. At least one processor of the computing device, or a specialized hardware controller, may be configured to partition iterations of a repetitive process and assign the partitions to initialized tasks to be executed in parallel by a plurality of processor cores. Upon completing a task, remaining divisible partitions of the repetitive process of ongoing tasks may be subpartitioned and assigned to the ongoing task, and the completed task or a newly initialized task. Information about the iteration space for a repetitive process may be stored in a descriptor table, and status information for all partitions of a repetitive process stored in a status table. Each processor core may have an associated local table that tracks iteration execution of each task, and is synchronized with the status table.

Abstract translation: 实施例包括用于并行地重复处理的基于任务的处理的计算设备，系统和方法。 计算设备的至少一个处理器或专用硬件控制器可以被配置为分区重复过程的迭代，并且将分区分配给由多个处理器核并行执行的初始化任务。 完成任务后，正在执行的任务的重复进程的剩余可分区可以被分分区并分配给正在进行的任务，以及完成的任务或新初始化的任务。 关于重复过程的迭代空间的信息可以存储在描述符表中，以及存储在状态表中的重复进程的所有分区的状态信息。 每个处理器核心可以具有跟踪每个任务的迭代执行的相关联的本地表，并且与状态表同步。

公开(公告)号：US20150268993A1

公开(公告)日：2015-09-24

申请号：US14336288

申请日：2014-07-21

Applicant: QUALCOMM Incorporated

Inventor： Pablo Montesinos Ortego ,  Michael Weber ,  Han Zhao

IPC: G06F9/48 ,  G06F9/54

CPC classification number: G06F9/4881 ,  G06F8/452 ,  G06F9/44 ,  G06F9/485 ,  G06F9/5066 ,  G06F9/54

Abstract: Aspects include computing devices, systems, and methods for task-based handling of nested repetitive processes in parallel. At least one processor of the computing device may be configured to partition iterations of an outer repetitive process and assign the partitions to initialized tasks to be executed in parallel by a plurality of processor cores. A shadow task may be initialized for each task to execute iterations of an inner repetitive process. Upon completing a task, divisible partitions of the outer repetitive process of ongoing tasks may be subpartitioned and assigned to the ongoing task, and the completed task and shadow task or a newly initialized task and shadow task. Upon completing all but one task and one iteration of the outer repetitive process, shadow tasks may be initialized to execute partitions of iterations of the inner repetitive process.

Abstract translation: 方面包括并行执行嵌套重复过程的基于任务的处理的计算设备，系统和方法。 计算设备的至少一个处理器可以被配置为分配外部重复过程的迭代，并且将分区分配给由多个处理器核并行执行的初始化任务。 可以为每个任务初始化影子任务以执行内部重复过程的迭代。 完成任务后，正在执行的任务的外部重复进程的可分割分区可以被分区并分配给正在进行的任务，并且完成任务和影子任务或新初始化的任务和影子任务。 完成外部重复过程的所有除了一个任务和一个迭代之外，可以对影子任务进行初始化，以执行内部重复过程的迭代分区。

公开(公告)号：US10296074B2

公开(公告)日：2019-05-21

申请号：US15417605

申请日：2017-01-27

Applicant: QUALCOMM Incorporated

Inventor： Wenjia Ruan ,  Han Zhao ,  Tushar Kumar

IPC: G06F9/50 ,  G06F1/329 ,  G06F1/28 ,  G06F1/3228 ,  G06F9/48

Abstract: Various embodiments provide methods, devices, and non-transitory processor-readable storage media enabling joint goals, such as joint power and performance goals, to be realized on a per heterogeneous processing device basis for heterogeneous parallel computing constructs. Various embodiments may enable assignments of power states for heterogeneous processing devices on a per heterogeneous processing device basis to satisfy an overall goal on the heterogeneous processing construct. Various embodiments may enable dynamic adjustment of power states for heterogeneous processing devices on a per heterogeneous processing device basis.

公开(公告)号：US10169105B2

公开(公告)日：2019-01-01

申请号：US14992268

申请日：2016-01-11

Applicant: QUALCOMM Incorporated

Inventor： Han Zhao ,  Pablo Montesinos Ortego ,  Arun Raman ,  Behnam Robatmili ,  Gheorghe Calin Cascaval

IPC: G06F9/46 ,  G06F9/52 ,  G06F9/48

Abstract: Aspects include computing devices, systems, and methods for implementing scheduling and execution of lightweight kernels as simple tasks directly by a thread without setting up a task structure. A computing device may determine whether a task pointer in a task queue is a simple task pointer for the lightweight kernel. The computing device may schedule a first simple task for the lightweight kernel for execution by the thread. The computing device may retrieve, from an entry of a simple task table, a kernel pointer for the lightweight kernel. The entry in the simple task table may be associated with the simple task pointer. The computing device may directly execute the lightweight kernel as the simple task.

公开(公告)号：US20180060130A1

公开(公告)日：2018-03-01

申请号：US15245604

申请日：2016-08-24

Applicant: QUALCOMM Incorporated

Inventor： Arun Raman ,  Han Zhao ,  Aravind Natarajan

IPC: G06F9/50

CPC classification number: G06F9/5027 ,  G06F9/5066 ,  G06F2209/5017

Abstract: Embodiments include computing devices, apparatus, and methods implemented by the apparatus for implementing speculative loop iteration partitioning (SLIP) for heterogeneous processing devices. A computing device may receive iteration information for a first partition of iterations of a repetitive process and select a SLIP heuristic based on available SLIP information and iteration information for the first partition. The computing device may determine a split value for the first partition using the SLIP heuristic, and partition the first partition using the split value to produce a plurality of next partitions.

公开(公告)号：US20180052776A1

公开(公告)日：2018-02-22

申请号：US15239937

申请日：2016-08-18

Applicant: QUALCOMM Incorporated

Inventor： Han Zhao ,  Arun Raman ,  Aravind Natarajan

IPC: G06F12/109

CPC classification number: G06F12/109 ,  G06F2212/1041 ,  G06F2212/657

Abstract: Embodiments include computing devices, apparatus, and methods implemented by the apparatus for implementing shared virtual index translation on a computing device. The computing device may receive a base virtual address for storing an output of a kernel function execution to a dedicated memory and determine whether the virtual address is in a range of virtual addresses for a privatized output buffer within the dedicated memory, which may be smaller than the dedicated memory. The computing device may calculate a first modified physical address using a physical address mapped to the base virtual address and an offset of a first processing device associated with the dedicated memory in response to determining that the base virtual address is in the range of virtual addresses. The computing device may store the output of the kernel function execution to the privatized output buffer at the first modified physical address.

公开(公告)号：US20170031728A1

公开(公告)日：2017-02-02

申请号：US14992268

申请日：2016-01-11

Applicant: QUALCOMM Incorporated

Inventor： Han Zhao ,  Pablo Montesinos Ortego ,  Arun Raman ,  Behnam Robatmili ,  Gheorghe Calin Cascaval

IPC: G06F9/52

CPC classification number: G06F9/52 ,  G06F9/4843

Abstract: Aspects include computing devices, systems, and methods for implementing scheduling and execution of lightweight kernels as simple tasks directly by a thread without setting up a task structure. A computing device may determine whether a task pointer in a task queue is a simple task pointer for the lightweight kernel. The computing device may schedule a first simple task for the lightweight kernel for execution by the thread. The computing device may retrieve, from an entry of a simple task table, a kernel pointer for the lightweight kernel. The entry in the simple task table may be associated with the simple task pointer. The computing device may directly execute the lightweight kernel as the simple task.

Abstract translation: 方面包括计算设备，系统和方法，用于直接通过线程实现轻量级内核的调度和执行，而无需设置任务结构。 计算设备可以确定任务队列中的任务指针是否是轻量级内核的简单任务指针。 计算设备可以安排轻量级内核的第一简单任务以供线程执行。 计算设备可以从简单任务表的条目中检索轻量级内核的内核指针。 简单任务表中的条目可能与简单任务指针相关联。 计算设备可以直接执行轻量级内核作为简单任务。