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    Pseudo-CML latch and divider having reduced charge sharing between output nodes
    13.
    发明授权
    Pseudo-CML latch and divider having reduced charge sharing between output nodes 有权
    伪CML锁存器和分压器具有降低的输出节点之间的电荷共享

    公开(公告)号：US09059686B2

    公开(公告)日：2015-06-16

    申请号：US13926680

    申请日：2013-06-25

    Applicant: QUALCOMM Incorporated

    Inventor： Wu-Hsin Chen ,  Li Liu ,  Jianyun Hu

    IPC: H03K3/00 ,  H03K3/027 ,  H03K3/037 ,  H03K3/017 ,  H01L21/8238 ,  H03K3/356

    CPC classification number: H03K3/017 ,  H01L21/823871 ,  H03K3/356121 ,  H03K3/356139

    Abstract: In one example, a high-speed divider includes two identical pseudo-CML latches and four output inverters. Each latch includes a pair of cross-coupled signal holding transistors. A first P-channel pull-up circuit pulls up on a second output node QB of the latch. A second P-channel pull-up circuit pulls up on a first output node Q of the latch. A pull-down circuit involves four N-channel transistors. This pull-down circuit: 1) couples the QB node to ground when a clock signal CK is high and a data signal D is high, 2) couples the Q node to ground when CK is high and D is low, 3) prevents a transfer of charge between the QB and Q nodes through the pull-down circuit when D transitions during a time period when CK is low, and 4) decouples the QB and Q nodes from the pull-down circuit when CK is low.

    Abstract translation: 在一个示例中，高速分频器包括两个相同的伪CML锁存器和四个输出反相器。 每个锁存器包括一对交叉耦合的信号保持晶体管。 第一P沟道上拉电路在锁存器的第二输出节点QB上拉起。 第二P沟道上拉电路在锁存器的第一输出节点Q上拉起。 下拉电路包括四个N沟道晶体管。 该下拉电路：1）当时钟信号CK为高电平且数据信号D为高电平时，将QB节点耦合到地，2）当CK为高电平且D为低电平时将Q节点接地，3）防止 当CK为低电平时，D转换时，通过下拉电路在QB和Q节点之间传输电荷;以及4）当CK为低电平时，将QB和Q节点与下拉电路解耦。

    Intermediate frequency filter for millimeter-wave carrier aggregation
    14.
    发明授权
    Intermediate frequency filter for millimeter-wave carrier aggregation 有权

    公开(公告)号：US12267090B2

    公开(公告)日：2025-04-01

    申请号：US17934784

    申请日：2022-09-23

    Applicant: QUALCOMM Incorporated

    Inventor： Wu-Hsin Chen ,  Yunfei Feng ,  Vinod Panikkath ,  Li Liu ,  Sher Jiun Fang

    IPC: H04B1/00 ,  H03H7/01 ,  H04B1/10

    Abstract: Aspects of the disclosure relate to wireless communication apparatuses, methods, and other aspects of sliding intermediate frequency filters for carrier aggregation communications. One aspect a high band mixer including a radio frequency (RF) receive signal input, a local oscillator (LO) input, and an IF signal output, a tunable high pass filter including an input and an output, an intermediate frequency (IF) received signal multiplexer including a merged IF CA signal output, a first input, and a second input, an LO input, and an IF signal output, where the RF receive signal input is coupled to the low band mmW CA receive port, and a tunable low pass filter including an input and an output, where the input is coupled to the IF signal output of the low band mixer, and where the output is coupled to the second input of the IF received signal multiplexer.

    Swing tracking and control
    15.
    发明授权
    Swing tracking and control 有权

    公开(公告)号：US11025195B2

    公开(公告)日：2021-06-01

    申请号：US16375765

    申请日：2019-04-04

    Applicant: QUALCOMM Incorporated

    Inventor： Wu-Hsin Chen ,  Rui Xu ,  Marco Vigilante ,  Li Liu ,  Xiaotie Wu

    IPC: H03B5/12 ,  H03F3/195 ,  H03D7/00 ,  H03F3/347 ,  H03F3/193 ,  H03F3/45 ,  H03D7/12

    Abstract: In certain aspects, an apparatus includes a transformer including an input inductor and an output inductor, wherein the input inductor is magnetically coupled to the output inductor. The apparatus also includes a transconductance driver configured to drive the input inductor based on an input signal. The apparatus further includes a feedback circuit configured to detect an output voltage swing at the output inductor, generate a regulated voltage at the input inductor, and control the regulated voltage based on the detected output voltage swing.

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