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    Patched shading in graphics processing
    11.
    发明授权
    Patched shading in graphics processing 有权

    公开(公告)号：US11769294B2

    公开(公告)日：2023-09-26

    申请号：US17522178

    申请日：2021-11-09

    Applicant: QUALCOMM Incorporated

    Inventor： Vineet Goel ,  Andrew Evan Gruber ,  Donghyun Kim

    IPC: G06T15/80 ,  G06T17/20 ,  G06T15/00 ,  G06T15/50

    CPC classification number: G06T15/80 ,  G06T15/00 ,  G06T15/005 ,  G06T15/50 ,  G06T17/20

    Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.

    ADAPTIVE CONTEXT SWITCHING
    13.
    发明申请
    ADAPTIVE CONTEXT SWITCHING 审中-公开

    公开(公告)号：US20170221173A1

    公开(公告)日：2017-08-03

    申请号：US15009605

    申请日：2016-01-28

    Applicant: QUALCOMM Incorporated

    Inventor： Anirudh Rajendra Acharya ,  Alexei Vladimirovich Bourd ,  David Rigel Garcia Garcia ,  Milind Nilkanth Nemlekar ,  Vineet Goel

    IPC: G06T1/20

    CPC classification number: G06T1/20 ,  G06F9/4843 ,  G06F9/4887 ,  G06T2200/28

    Abstract: A graphics processing unit (GPU) may dispatch a first set of commands for execution on one or more processing units of the GPU. The GPU may receive notification from a host device indicating that a second set of commands are ready to execute on the GPU. In response, the GPU may issue a first preemption command at a first preemption granularity to the one or more processing units. In response to the GPU failing to preempt execution of the first set of commands within an elapsed time period after issuing the first preemption command, the GPU may issue a second preemption command at a second preemption granularity to the one or more processing units, where the second preemption granularity is finer-grained than the first preemption granularity.

    Techniques for conservative rasterization
    16.
    发明授权
    Techniques for conservative rasterization 有权
    保守光栅化技术

    公开(公告)号：US09324127B2

    公开(公告)日：2016-04-26

    申请号：US14454394

    申请日：2014-08-07

    Applicant: QUALCOMM Incorporated

    Inventor： Ouns Mouri ,  Vineet Goel ,  Tao Wang

    IPC: G06T1/20 ,  G06T17/10 ,  G09G5/18

    CPC classification number: G06T1/20 ,  G06T11/40 ,  G06T17/10 ,  G09G5/18 ,  G09G2310/08

    Abstract: This disclosure describes a method for performing conservative rasterization in a processor comprising determining vertices of a primitive, defining edges of the primitive by determining a set of edge equations based on the determined vertices, wherein the edge equations are based on an edge shifting parameter plus an offset, determining pixels that touch the edges of the primitive using the determined edge equations, and rasterizing the primitive using the determined pixels.

    Abstract translation: 本公开描述了一种用于在处理器中执行保守光栅化的方法，包括通过基于所确定的顶点确定一组边缘方程来确定原语的边缘来定义基元的边缘，其中边缘方程基于边缘移位参数加上 使用所确定的边缘方程来确定触摸图元的边缘的像素，以及使用所确定的像素来对原图进行光栅化。

    RAY-BOX INTERSECTION TESTING USING DOT PRODUCT-BASED FIXED FUNCTION LOGIC
    17.
    发明申请
    RAY-BOX INTERSECTION TESTING USING DOT PRODUCT-BASED FIXED FUNCTION LOGIC 有权
    使用基于产品的固定功能逻辑的RAY-BOX接口测试

    公开(公告)号：US20160110910A1

    公开(公告)日：2016-04-21

    申请号：US14517706

    申请日：2014-10-17

    Applicant: QUALCOMM Incorporated

    Inventor： Juraj Obert ,  Vineet Goel

    IPC: G06T15/06 ,  G06T15/04 ,  G06T15/80 ,  G06T15/00

    CPC classification number: G06T15/06 ,  G06T15/005 ,  G06T15/04 ,  G06T15/80 ,  G06T2200/28

    Abstract: A method and apparatus for ray tracing may include using texture pipeline hardware of a GPU to perform ray intersection testing for a first ray and a first shape. Using the texture pipeline hardware to perform ray intersection testing may include calculating a plurality of dot products with the texture pipeline hardware, and determining whether the first ray intersects the first shape based on the plurality of dot products.

    Abstract translation: 用于光线跟踪的方法和装置可以包括使用GPU的纹理管线硬件来执行第一射线和第一形状的射线相交测试。 使用纹理管线硬件执行射线相交测试可以包括使用纹理管线硬件来计算多个点积，并且基于多个点积来确定第一射线是否与第一形状相交。

    Multi-primitive graphics rendering pipeline
    19.
    发明授权
    Multi-primitive graphics rendering pipeline 有权
    多原始图形渲染管道

    公开(公告)号：US09177351B2

    公开(公告)日：2015-11-03

    申请号：US13842017

    申请日：2013-03-15

    Applicant: QUALCOMM Incorporated

    Inventor： Vineet Goel ,  Young In Yeo

    IPC: G06T15/00 ,  G06T1/20 ,  G06T17/20

    CPC classification number: G06T1/20 ,  G06T15/005 ,  G06T17/20

    Abstract: This disclosure describes techniques for rendering a plurality of primitives that includes at least two different types of primitives during the execution of a single draw call command. This disclosure also describes techniques for rendering a plurality of primitives using tessellation domains of different tessellation domain types during the execution of a single draw call command. The techniques of this disclosure may, in some examples, reduce the complexity and processing overhead for user applications, reduce the number of times that the rendering state of the graphics rendering pipeline needs to be switched during the drawing of a graphics scene, and/or reduce the number of times that shader programs need to be reloaded into different processing stages of a graphics pipeline during the rendering of a graphics scene.

    Abstract translation: 本公开描述了在执行单次绘制调用命令期间渲染包括至少两种不同类型的图元的多个图元的技术。 本公开还描述了在执行单个绘制调用命令期间使用不同镶嵌域类型的镶嵌域渲染多个图元的技术。 在一些示例中，本公开的技术可以降低用户应用的复杂性和处理开销，减少在图形场景绘制期间需要切换图形呈现管线的渲染状态的次数，和/或 减少在渲染图形场景期间着色器程序需要重新加载到图形管道的不同处理阶段的次数。

    Output ordering of domain coordinates for tessellation
    20.
    发明授权
    Output ordering of domain coordinates for tessellation 有权
    用于细分的域坐标的输出顺序

    公开(公告)号：US09123168B2

    公开(公告)日：2015-09-01

    申请号：US13754005

    申请日：2013-01-30

    Applicant: QUALCOMM Incorporated

    Inventor： Chunhui Mei ,  Nariman Moezzi Madani ,  Vineet Goel ,  Usame Ceylan ,  Guofang Jiao

    IPC: G06T15/30 ,  G06T17/20 ,  G06T15/00

    CPC classification number: G06T17/20 ,  G06T15/005

    Abstract: Systems and methods for a tessellation are described. For tessellation, a tessellation unit may divide a domain into a plurality of portions, where at least one portion is a contiguous portion. The tessellation unit may output domain coordinates of primitives along diagonal strips within the contiguous portion to increase the likelihood that patch coordinates that correspond to the domain coordinates are stored in a reuse buffer.

    Abstract translation: 描述了细分的系统和方法。 为了细分，镶嵌单元可以将域划分成多个部分，其中至少一个部分是连续部分。 细分单元可以输出连续部分内沿着对角条纹的基元的域坐标，以增加对应于域坐标的修补坐标被存储在重用缓冲器中的可能性。

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