公开(公告)号：US09026681B2

公开(公告)日：2015-05-05

申请号：US13962770

申请日：2013-08-08

Applicant: QUALCOMM Incorporated

Inventor： Hee-Jun Park ,  Alex Kuang-Hsuan Tu ,  Thomas Andrew Sartorius ,  Richard Gerard Hofmann ,  Thomas Andrew Morison

IPC: G06F13/38 ,  G06F3/00 ,  G06F13/10

CPC classification number: G06F13/385 ,  G06F3/00 ,  G06F9/5094 ,  G06F13/10 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/22

Abstract: A system is disclosed for mapping operating-system-identified addresses for substantially-identical hardware modules into performance-parameter-based addresses for the hardware modules. The mapping is accomplished by configuring a flexible I/O interface responsive to a characterization of at least one performance parameter for each hardware module.

Abstract translation: 公开了一种用于将用于基本上相同的硬件模块的操作系统识别的地址映射到用于硬件模块的基于性能参数的地址的系统。 映射是通过配置灵活的I / O接口来实现的，该接口响应于每个硬件模块的至少一个性能参数的表征。

公开(公告)号：US09514061B1

公开(公告)日：2016-12-06

申请号：US14716947

申请日：2015-05-20

Applicant: QUALCOMM Incorporated

Inventor： Henry Arthur Pellerin, III ,  Thomas Philip Speier ,  Thomas Andrew Sartorius ,  Michael William Morrow ,  James Norris Dieffenderfer ,  Kenneth Alan Dockser ,  Michael Scott McIlvaine

IPC: G06F12/00 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F12/128 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0895 ,  G06F2212/1016 ,  G06F2212/401 ,  G06F2212/6032 ,  G06F2212/621

Abstract: A memory structure compresses a portion of a memory tag using an indexed tag compression structure. A set of higher order bits of the memory tag may be stored in the indexed tag compression structure, where the set of higher order bits are identified by an index value. A tag array stores a set of lower order bits of the memory tag and the index value identifying the entry in the tag compression structure storing the set of higher order bits of the memory tag. The memory tag may comprise at least a portion of a memory address of a data element stored in a data array.

Abstract translation: 存储器结构使用索引标签压缩结构压缩存储器标签的一部分。 存储器标签的一组较高位可以存储在索引标签压缩结构中，其中较高位的集合由索引值标识。 标签阵列存储存储器标签的一组较低位，以及标识在存储标签的较高位的集合的标签压缩结构中的条目的索引值。 存储器标签可以包括存储在数据阵列中的数据元素的存储器地址的至少一部分。

公开(公告)号：US09292442B2

公开(公告)日：2016-03-22

申请号：US13933337

申请日：2013-07-02

Applicant: QUALCOMM Incorporated

Inventor： Thomas Philip Speier ,  Eric F. Robinson ,  Jaya Prakash Subramaniam Ganasan ,  Thomas Andrew Sartorius ,  James Norris Dieffenderfer

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/0831 ,  G06F15/173

Abstract: Techniques are described for a multi-processor having two or more processors that increases the opportunity for a load-exclusive command to take a cache line in an Exclusive state, which results in increased performance when a store-exclusive is executed. A new bus operation read prefer exclusive is used as a hint to other caches that a requesting master is likely to store to the cache line, and, if possible, the other cache should give the line up. In most cases, this will result in the other master giving the line up and the requesting master taking the line Exclusive. In most cases, two or more processors are not performing a semaphore management sequence to the same address at the same time. Thus, a requesting master's load-exclusive is able to take a cache line in the Exclusive state an increased number of times.

Abstract translation: 针对具有两个或多个处理器的多处理器描述技术，这增加了独占命令以独占状态取高速缓存行的机会，这导致执行存储排他时的性能提高。 读取优先排序的新总线操作被用作对请求主机可能存储到高速缓存行的其他高速缓存的提示，并且如果可能的话，其他高速缓存应该给排队。 在大多数情况下，这将导致其他主人员排队，并且请求主人将线独占。 在大多数情况下，两个或多个处理器不会同时对同一地址执行信号量管理序列。 因此，请求主机的负载排他能够在独占状态下取高速缓存行增加次数。

公开(公告)号：US20150046604A1

公开(公告)日：2015-02-12

申请号：US13962770

申请日：2013-08-08

Applicant: QUALCOMM Incorporated

Inventor： Hee-Jun Park ,  Alex Kuang-Hsuan Tu ,  Thomas Andrew Sartorius ,  Richard Gerard Hofmann ,  Thomas Andrew Morison

IPC: G06F13/38

CPC classification number: G06F13/385 ,  G06F3/00 ,  G06F9/5094 ,  G06F13/10 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/22

Abstract: A system is disclosed for mapping operating-system-identified addresses for substantially-identical hardware modules into performance-parameter-based addresses for the hardware modules. The mapping is accomplished by configuring a flexible I/O interface responsive to a characterization of at least one performance parameter for each hardware module.

Abstract translation: 公开了一种用于将用于基本上相同的硬件模块的操作系统识别的地址映射到用于硬件模块的基于性能参数的地址的系统。 映射是通过配置灵活的I / O接口来实现的，该接口响应于每个硬件模块的至少一个性能参数的表征。