公开(公告)号：US10447280B2

公开(公告)日：2019-10-15

申请号：US15711708

申请日：2017-09-21

Applicant: Qualcomm Incorporated

Inventor： Ayush Mittal ,  Gajanan Maroti Devpuje ,  Bhushan Shanti Asuri ,  Krishnaswamy Thiagarajan

IPC: H03L7/06 ,  H03L7/07 ,  H03L7/081 ,  H03K5/133 ,  H03L7/099 ,  H03L7/089 ,  H03L7/093

Abstract: An integrated circuit is disclosed that implements a delay-locked loop with differential delay lines. In an example aspect, the integrated circuit includes a first delay line, a second delay line, and control circuitry. The first and second delay lines are coupled to a reference clock source to receive a reference clock. The first delay line produces a first delayed signal that is delayed relative to the reference clock by a first delay amount. The second delay line produces a second delayed signal that is delayed relative to the reference clock by a second delay amount. The control circuitry is coupled to the first and second delay lines. The control circuitry is configured to receive the first delayed signal, to receive the second delayed signal, and to adjust the first delay amount or the second delay amount based on the first delayed signal and the second delayed signal.

公开(公告)号：US10348528B2

公开(公告)日：2019-07-09

申请号：US15472454

申请日：2017-03-29

Applicant: QUALCOMM Incorporated

Inventor： Ayush Mittal ,  Bhushan Shanti Asuri ,  Krishnaswamy Thiagarajan ,  Sameer Vasantlal Vora ,  Mahim Ranjan

IPC: H04L25/03 ,  H04L27/36 ,  H03D7/14 ,  H04B1/04 ,  H03D7/16 ,  H03H7/21 ,  H03H7/01

Abstract: A system includes: a baseband phase generator configured to receive differential in-phase (I) and quadrature (Q) signals and configured to output N phase-shifted baseband signals, wherein N is greater than 4, further wherein the baseband phase generator comprises a plurality of notch filters configured to receive the I and Q signals; and an upconverter configured to receive the phase-shifted baseband signals, to perform mixing on the phase-shifted baseband signals, and to output a differential upconverted signal.