公开(公告)号：US09754923B1

公开(公告)日：2017-09-05

申请号：US15149646

申请日：2016-05-09

Applicant: QUALCOMM Incorporated

Inventor： Jing Xie ,  Kambiz Samadi ,  Pratyush Kamal ,  Yang Du ,  Javid Jaffari

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  G06F17/50 ,  H01L23/48 ,  H01L27/06

CPC classification number: H01L25/0657 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/78 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L24/13 ,  H01L25/16 ,  H01L27/0688 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1434

Abstract: Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs) are disclosed. Exemplary aspects of the present disclosure contemplate consolidating power gating circuits or cells into a single tier within a 3DIC. Still further, the power gating circuits are consolidated in a tier closest to a voltage source. This closest tier may include a backside metal layer that allows a distance between the voltage source and the power gating circuits to be minimized. By minimizing the distance between the voltage source and the power gating circuits, power loss from routing elements therebetween is minimized. Further, by consolidating the power gating circuits in a single tier, routing distances between the power gating circuits and downstream elements may be minimized and power loss from those routing elements are minimized. Other advantages are likewise realized by placement of the power gating circuits according to exemplary aspects of the present disclosure.

公开(公告)号：US09741691B2

公开(公告)日：2017-08-22

申请号：US14698842

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Kambiz Samadi ,  Yang Du

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/528 ,  H01L27/06 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/05147 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/73153 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Systems and methods relate to power delivery networks (PDNs) for monolithic three-dimensional integrated circuits (3D-ICs). A monolithic 3D-IC includes a first die adjacent to and in contact with power/ground bumps. A second die is stacked on the first die, the second die separated from the power/ground bumps by the first die. One or more bypass power/ground vias and one or more monolithic inter-tier vias (MIVs) are configured to deliver power from the power/ground bumps to the second die.

公开(公告)号：US09626311B2

公开(公告)日：2017-04-18

申请号：US14602505

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Karamvir Singh Chatha ,  Yang Du ,  Kambiz Samadi

IPC: G06F13/16 ,  H01L25/065 ,  G06F13/42 ,  H01L23/48 ,  H01L23/50 ,  H01L25/18 ,  H01L25/00 ,  H01L27/06

CPC classification number: G06F13/1684 ,  G06F13/1605 ,  G06F13/4282 ,  H01L23/481 ,  H01L23/50 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06544

Abstract: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.

公开(公告)号：US20160217087A1

公开(公告)日：2016-07-28

申请号：US14602505

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Karamvir Singh Chatha ,  Yang Du ,  Kambiz Samadi

IPC: G06F13/16 ,  H01L25/065 ,  G06F13/42 ,  H01L25/00 ,  H01L23/50 ,  H01L23/48 ,  H01L25/18

CPC classification number: G06F13/1684 ,  G06F13/1605 ,  G06F13/4282 ,  H01L23/481 ,  H01L23/50 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06544

Abstract: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.

Abstract translation: 在详细描述中公开的方面包括采用分布式硅通孔（TSV）农场的三维（3D）集成电路（IC）（3DIC）中的存储器控​​制器放置。 在这方面，在一方面，存储器控制器基于分布式TSV场内的集中式存储器控制器放置方案而设置在3DIC中。 存储器控制器可以放置在多个TSV农场中的几何中心处，以在存储器控制器和多个TSV农场中的每一个之间提供大致相等的线长度。 在另一方面，基于分布式存储器控制器放置方案在3DIC中提供多个存储器控制器，其中多个存储器控制器中的每一个与多个TSV农场中的相应TSV场相邻放置。 通过在3DIC中基于集中式存储器控制器放置方案和/或分布式存储器控制器放置方案布置存储器控制器，存储器访问请求的等待时间最小化。

公开(公告)号：US20150103866A1

公开(公告)日：2015-04-16

申请号：US14091390

申请日：2013-11-27

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Yang Du ,  Mehdi Saeidi

IPC: G01K7/42 ,  G01K1/02

CPC classification number: G01K7/427 ,  G01K1/022 ,  G01K2217/00

Abstract: Embodiments disclosed in the detailed description include digital temperature estimators (DTEs) disposed in integrated circuits (ICs) for estimating temperature within the ICs. Related systems and methods are also disclosed. In one embodiment, the DTEs can be used to estimate temperatures in an IC by implementing a temperature estimation model (TEM). The TEM can provide an estimated temperature of an IC block disposed in the IC based on activity event(s) associated with the IC block, as opposed to providing temperature sensors in the IC to measure temperature of the IC block directly. The DTEs can be operated in real time so that power and/or thermal regulation systems of the IC can obtain accurate and reliable temperature estimation from the DTEs. In this manner, thermal dissipation in the IC may be regulated more effectively.

Abstract translation: 在详细描述中公开的实施例包括设置在用于估计IC内的温度的集成电路（IC）中的数字温度估计器（DTE）。 还公开了相关系统和方法。 在一个实施例中，DTE可用于通过实施温度估计模型（TEM）来估计IC中的温度。 与在IC中提供温度传感器以直接测量IC块的温度相反，TEM可以基于与IC块相关联的活动事件来提供设置在IC中的IC块的估计温度。 DTE可以实时操作，使得IC的功率和/或热调节系统可以从DTE获得准确可靠的温度估计。 以这种方式，可以更有效地调节IC中的散热。

公开(公告)号：US20190122973A1

公开(公告)日：2019-04-25

申请号：US16220764

申请日：2018-12-14

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad Amar Panth ,  Yang Du ,  Robert Philip Gilmore

IPC: H01L23/498 ,  G06F17/50 ,  H01L21/768

CPC classification number: H01L23/49827 ,  G06F17/5068 ,  H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

公开(公告)号：US09929733B1

公开(公告)日：2018-03-27

申请号：US15437871

申请日：2017-02-21

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Kambiz Samadi ,  Jing Xie ,  Yang Du

IPC: H01L23/522 ,  H03K19/094 ,  H01L23/528 ,  H01L27/06 ,  H01L27/118

CPC classification number: H03K19/094 ,  G06F17/505 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/11807 ,  H01L2027/11851 ,  H01L2027/11872 ,  H01L2027/11875

Abstract: A 3D integrated circuit reduces delay when a signal traverses logical blocks of the integrated circuit. In one instance, the 3D integrated circuit has a first tier and a second tier including one or more first and second logical blocks, respectively. The first logical block(s) include a first primary output logic gate, a first primary input logic gate, a first primary input pin and a first primary output pin. The first primary output pin lies within a perimeter defined by a total area occupied by logic gates of the first logical block(s). The second logical block(s) include a second primary output logic gate, a second primary input logic gate, a second primary input pin and a second primary output pin. The second primary input pin is coupled to the first primary output pin.

公开(公告)号：US20150333005A1

公开(公告)日：2015-11-19

申请号：US14795914

申请日：2015-07-10

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad Amar Panth ,  Pratyush Kamal ,  Yang Du

IPC: H01L23/522 ,  G06F17/50 ,  H01L27/06

CPC classification number: H01L23/5226 ,  G06F17/5072 ,  G06F17/5081 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan.

Abstract translation: 公开了使用聚类来增加可用空白位置的单片三维（3D）集成电路（IC）（3DIC）中的单片间通道（MIV））。 在一个实施例中，提供了使用聚类将MIV放置在单片3DIC中的方法。 该方法包括确定在初始3DIC布局图中是否有多个MIV的多个初始MIV布置内是否包括任何MIV布局群集。 该方法还包括在初始3DIC布局图中的每个MIV放置簇内的多个MIV中的每个MIV在每个MIV放置簇的最终MIV放置处对齐以提供聚集的3DIC布局图。

公开(公告)号：US09064077B2

公开(公告)日：2015-06-23

申请号：US13792384

申请日：2013-03-11

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Yang Du

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/66

Abstract: The disclosed embodiments are directed to systems and method for floorplanning an integrated circuit design using a mix of 2D and 3D blocks that provide a significant improvement over existing 3D design methodologies. The disclosed embodiments provide better floorplan solutions that further minimize wirelength and improve the overall power/performance envelope of the designs. The disclosed methodology may be used to construct new 3D IP blocks to be used in designs that are built using monolithic 3D integration technology.

Abstract translation: 所公开的实施例涉及用于使用提供对现有3D设计方法的显着改进的2D和3D块的混合来布局规划集成电路设计的系统和方法。 所公开的实施例提供了更好的平面图解决方案，其进一步最小化电线长度并提高设计的整体功率/性能包络。 所公开的方法可以用于构建新的3D IP块，以用于使用单片3D集成技术构建的设计中。

公开(公告)号：US20150112646A1

公开(公告)日：2015-04-23

申请号：US14132377

申请日：2013-12-18

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du ,  Kambiz Samadi

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/06

Abstract: Methods of designing three dimensional integrated circuits (3DIC) and related systems and components are disclosed. An exemplary embodiment provides an improved cell library for use with existing place and route software in such a manner that the modified software allows building 3DICs. The improved cell library includes 3D cells that have the footprint of the cell projected onto a two dimensional (2D) image. The projected view may then be discounted to the portion of the cell that is within an upper tier so that the cell appears to the place and route software to be a 2D cell. The discounted 2D image is then used by the place and route software. Such cells allow a circuit designer to leverage the existing 2D place and route tools as well as static timing analysis tools.

Abstract translation: 公开了设计三维集成电路（3DIC）及相关系统和组件的方法。 示例性实施例提供了一种改进的小区库，其用于与现有的位置和路由软件一起使用，使得修改的软件允许构建3DIC。 改进的细胞库包括具有投影到二维（2D）图像上的细胞的足迹的3D细胞。 然后可以将投影视图折扣到上层内的单元的部分，使得单元格出现在该位置并将软件路由为2D单元。 打折的2D图像然后由地方和路线软件使用。 这样的单元允许电路设计者利用现有的2D位置和路径工具以及静态时序分析工具。