公开(公告)号：US09673787B2

公开(公告)日：2017-06-06

申请号：US14861503

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Lipeng Cao ,  Jeffrey Gemar ,  Ramaprasath Vilangudipitchai

IPC: H03K3/012 ,  H03K3/3562 ,  H03K3/037 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/0372 ,  H03K3/356008 ,  H03K3/3562

Abstract: Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip-flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rail. The IC further includes a flip-flop and power multiplexing circuitry. The flip flop includes a master portion and a slave portion. The master portion is coupled to the first power rail for a regular operational mode and for a retention operational mode. The power multiplexing circuitry is configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode.

公开(公告)号：US20250103130A1

公开(公告)日：2025-03-27

申请号：US18475371

申请日：2023-09-27

Applicant: QUALCOMM Incorporated

Inventor： Mahadevamurty Nemani ,  Matthew Severson ,  Gabriel Watkins ,  Vijayakumar Ashok Dibbad ,  Ronald Alton ,  Lai Xu ,  Jeffrey Gemar

IPC: G06F1/3296 ,  G06F1/3206

Abstract: Power limiting in a processor-based system based on allocating power budgets for different sub-systems based on multiple time-based power limits is disclosed. The processor-based system has multiple power consuming sub-systems (e.g., non-processing unit (PU) and PU sub-systems) that demand and consume power from a power source of the processor-based system. To limit overall power consumption of the processor-based system over different time-based power limits, the processor-based system includes a power limiter circuit. The power limiter circuit is configured to manage multiple, different time-based (e.g., time constant) power limits for the processor-based system and to allocate corresponding power limit budgets to constrain power consumption of different sub-systems based on the multiple time-based power limits. The power limiter circuit can be configured to constrain power consumption of a PU sub-system to a total PU sub-system power limit budget based on the multiple time-based power limits.

公开(公告)号：US20230359373A1

公开(公告)日：2023-11-09

申请号：US17661810

申请日：2022-05-03

Applicant: QUALCOMM Incorporated

Inventor： Engin Ipek ,  Hamza Omar ,  Bohuslav Rychlik ,  Saumya Ranjan Kuanr ,  Behnam Dashtipour ,  Michael Hawjing Lo ,  Jeffrey Gemar ,  Matthew Severson ,  George Patsilaras ,  Andrew Edmund Turner

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0673

Abstract: Selective refresh techniques for memory devices are disclosed. In one aspect, a memory device that is used with an application that has frequent repeated read or write commands to certain memory segments may be able to set a flag or similar indication that exempts these certain memory segments from being actively refreshed. By exempting these memory segments from being actively refreshed, these memory segments are continuously available, thereby improving performance. Likewise, because these memory segments are so frequently the subject of a read or write command, these memory segments are indirectly refreshed through the execution of the read or write command.

公开(公告)号：US11435804B2

公开(公告)日：2022-09-06

申请号：US16790431

申请日：2020-02-13

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Gemar ,  Ambudhar Tripathi ,  Philippe Martin

IPC: G06F1/3228 ,  G06F1/04 ,  G06F15/78 ,  G06F13/16 ,  G06F1/3246

Abstract: In some aspects, the present disclosure provides a method for power management. The method includes receiving, by a power management unit (PMU), signaling indicative of a first plurality of latency durations from a first plurality of clients, each of the first plurality of latency durations corresponding to one of the first plurality of clients, wherein each of the first plurality of clients is configured to utilize a first shared resource for communication of data. In certain aspects, the method also includes selecting, by the PMU, a first latency duration from the first plurality of latency durations based on a determination that the first latency duration is the shortest latency duration of the first plurality of latency durations, and transitioning, by the PMU, the first shared resource from an active state to the first idle state.

公开(公告)号：US09817470B2

公开(公告)日：2017-11-14

申请号：US15052786

申请日：2016-02-24

Applicant: QUALCOMM Incorporated

Inventor： Suresh Sugumar ,  Jeffrey Gemar ,  Ali Taha ,  Amy Derbyshire ,  Tao Xue ,  Mohammad Tamjidi ,  Rajat Mittal

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3885 ,  Y02D10/152

Abstract: An apparatus includes a first circuit and a second circuit sharing an instruction stream. A voltage controller circuit is configured to provide an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream. In another aspect, a method of operating a power management function is presented. The method includes providing an instruction stream for a first circuit and a second circuit and providing selectively an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream.