公开(公告)号：US11176734B1

公开(公告)日：2021-11-16

申请号：US17064188

申请日：2020-10-06

Applicant: QUALCOMM Incorporated

Inventor： Srihari Babu Alla ,  Adimulam Ramesh Babu ,  Jonnala Gadda Nagendra Kumar ,  Avinash Seetharamaiah ,  Tao Wang ,  Xuefeng Tang ,  Thomas Edwin Frisinger ,  Andrew Evan Gruber

IPC: G06T15/40 ,  G06T15/00

Abstract: The present disclosure relates to methods and apparatus for graphics processing. An example method generally includes receiving, at a graphics processing unit (GPU), a plurality of commands corresponding to a plurality of draws across a frame, each of the plurality of commands indicating a depth test direction with respect to a low-resolution depth (LRZ) buffer for the corresponding draw. The method generally includes maintaining, at the GPU, a LRZ status buffer to store a corresponding depth test direction for a first command in time of the plurality of commands processed by the GPU. The method generally includes disabling, at the GPU, use of the LRZ buffer for depth testing for any of the plurality of commands remaining unprocessed after processing a command of the plurality of commands having a different depth test direction than the corresponding depth test direction stored in the LRZ status buffer.

公开(公告)号：US20210200255A1

公开(公告)日：2021-07-01

申请号：US16729765

申请日：2019-12-30

Applicant: QUALCOMM Incorporated

Inventor： Srihari Babu ALLA ,  Murat Balci ,  Avinash Seetharamaiah ,  Jonnala Gadda Nagendra Kumar

IPC: G06F1/08 ,  G06T1/20

Abstract: Methods, systems, and devices for processing are described. In some devices, a command processor (CP) block may determine a first workload type for processing by a graphics processing unit (GPU). The first workload type may be a low power-consuming workload type or a high power-consuming workload type. The CP block may signal a request to a graphics power management unit (GMU) of the GPU to update the upper clock rate of the GPU while processing the first workload type. The GMU may configure the upper clock rate of the GPU based on the request from the CP block and a current limit of the device, and the GPU may process the first workload type based on using the updated upper clock rate.

公开(公告)号：US20160148338A1

公开(公告)日：2016-05-26

申请号：US15012467

申请日：2016-02-01

Applicant: QUALCOMM Incorporated

Inventor： Murat Balci ,  Christopher Paul Frascati ,  Avinash Seetharamaiah

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06T15/005

Abstract: The present disclosure provides systems and methods for multi-path rendering on tile based architectures including executing, with a graphics processing unit (GPU), a query pass, executing, with the GPU, a condition true pass based on the query pass without executing a flush operation, executing, with the GPU, a condition false pass based on the query pass without executing a flush operation, and responsive to executing the condition true pass and the condition false pass, executing, with the GPU, a flush operation.

公开(公告)号：US09286649B2

公开(公告)日：2016-03-15

申请号：US14059076

申请日：2013-10-21

Applicant: QUALCOMM Incorporated

Inventor： Murat Balci ,  Christopher Paul Frascati ,  Avinash Seetharamaiah

IPC: G06T15/40 ,  G06T1/20 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06T15/005

Abstract: A GPU may determine, based on a visibility stream, whether to execute instructions stored in an indirect buffer. The instructions include instructions for rendering primitives associated with a bin of a plurality of bins and include one or more secondary operations. The visibility stream indicate if one or more of the primitives associated with the bin will be visible in a finally rendered scene. The GPU may, responsive to determining not to execute the instructions stored in the indirect buffer, execute one or more secondary operations stored in a shadow indirect buffer. The GPU may, responsive to determining to execute the instructions stored in the indirect buffer, execute the instructions for rending the primitives associated with the bin of the plurality of bins and executing the one or more secondary operations stored in the indirect buffer.

Abstract translation: GPU可以基于可见性流来确定是否执行存储在间接缓冲器中的指令。 所述指令包括用于呈现与多个箱体的仓相关联的基元的指令，并且包括一个或多个次要操作。 可见性流指示与最后呈现的场景中是否可以看到与该仓相关联的一个或多个图元。 GPU可以响应于确定不执行存储在间接缓冲器中的指令，执行存储在阴影间接缓冲器中的一个或多个次要操作。 GPU可以响应于确定执行存储在间接缓冲器中的指令，执行用于重现与多个箱体的仓相关联的图元的指令，并执行存储在间接缓冲器中的一个或多个二次操作。

公开(公告)号：US09280956B2

公开(公告)日：2016-03-08

申请号：US13688748

申请日：2012-11-29

Applicant: QUALCOMM Incorporated

Inventor： Avinash Seetharamaiah ,  Christopher Paul Frascati

IPC: G09G5/393 ,  G09G5/00 ,  G06T1/60 ,  G06T15/00

CPC classification number: G09G5/393 ,  G06T1/60 ,  G06T15/005 ,  G09G5/001

Abstract: Systems and methods are described including creating a mask that indicates which pixel groups do not need to be loaded from Graphics Memory (GMEM). The mask indicates a pixel group does not need to be loaded from GMEM. The systems and methods may further include rendering a tile on a screen. This may include loading the GMEM based on the indication from the mask and skipping a load from the GMEM based on the indication from the mask.

Abstract translation: 描述了系统和方法，包括创建指示不需要从图形存储器（GMEM）加载哪些像素组的掩码。 掩码表示不需要从GMEM加载像素组。 系统和方法还可以包括在屏幕上渲染瓦片。 这可以包括基于掩码的指示加载GMEM，并基于掩码的指示从GMEM跳过负载。

公开(公告)号：US20140354661A1

公开(公告)日：2014-12-04

申请号：US14059076

申请日：2013-10-21

Applicant: QUALCOMM Incorporated

Inventor： Murat Balci ,  Christopher Paul Frascati ,  Avinash Seetharamaiah

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06T15/005

Abstract: A GPU may determine, based on a visibility stream, whether to execute instructions stored in an indirect buffer. The instructions include instructions for rendering primitives associated with a bin of a plurality of bins and include one or more secondary operations. The visibility stream indicate if one or more of the primitives associated with the bin will be visible in a finally rendered scene. The GPU may, responsive to determining not to execute the instructions stored in the indirect buffer, execute one or more secondary operations stored in a shadow indirect buffer. The GPU may, responsive to determining to execute the instructions stored in the indirect buffer, execute the instructions for rending the primitives associated with the bin of the plurality of bins and executing the one or more secondary operations stored in the indirect buffer.

Abstract translation: GPU可以基于可见性流来确定是否执行存储在间接缓冲器中的指令。 所述指令包括用于呈现与多个箱体的仓相关联的基元的指令，并且包括一个或多个次要操作。 可见性流指示与最后呈现的场景中是否可以看到与该仓相关联的一个或多个图元。 GPU可以响应于确定不执行存储在间接缓冲器中的指令，执行存储在阴影间接缓冲器中的一个或多个次要操作。 GPU可以响应于确定执行存储在间接缓冲器中的指令，执行用于重现与多个箱体的仓相关联的图元的指令，并执行存储在间接缓冲器中的一个或多个二次操作。

公开(公告)号：US11893677B1

公开(公告)日：2024-02-06

申请号：US17816375

申请日：2022-07-29

Applicant: QUALCOMM Incorporated

Inventor： Adimulam Ramesh Babu ,  Srihari Babu Alla ,  Avinash Seetharamaiah ,  Jonnala Gadda Nagendra Kumar ,  David Kirk McAllister

IPC: G06T15/06 ,  G06T17/10 ,  G06T17/00 ,  G06T15/08

CPC classification number: G06T15/06 ,  G06T15/08 ,  G06T17/005 ,  G06T17/10

Abstract: Systems and techniques are provided for widening a hierarchical structure for ray tracing. For instance, a process can include obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure and determining one or more candidate hierarchical acceleration data structures each including the plurality of primitives. A cost metric can be determined for the one or more candidate hierarchical acceleration data structures and, based on the cost metric, a compressibility prediction associated with a candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures can be determined. An output hierarchical acceleration data structure can be generated based on the compressibility prediction.

公开(公告)号：US20220122214A1

公开(公告)日：2022-04-21

申请号：US17071888

申请日：2020-10-15

Applicant: QUALCOMM Incorporated

Inventor： Thomas Edwin Frisinger ,  Richard Hammerstone ,  Jonnala Gadda Nagendra Kumar ,  Avinash Seetharamaiah ,  Shangmei Yu ,  Srihari Babu Alla

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/48

Abstract: Methods, systems, and devices for graphics processer unit (GPU) operations are described. A device may monitor one or more states of a GPU during a duration. Based on monitoring the one or more GPU states, the device may determine an execution of a GPU command that is common to at least two GPU operations for clearing the GPU buffer. The device may determine whether the GPU clear command has previously been executed during a duration or a GPU cycle in which the device monitored the GPU states. The device may process the GPU clear command based on the determination of whether the GPU clear command has previously been executed. For example, the device may drop the GPU clear command based on the determination or modify a portion of the GPU clear command and execute at least the modified portion of the GPU clear command.

公开(公告)号：US11087431B2

公开(公告)日：2021-08-10

申请号：US16694956

申请日：2019-11-25

Applicant: QUALCOMM Incorporated

Inventor： Srihari Babu Alla ,  Jonnala Gadda Nagendra Kumar ,  Avinash Seetharamaiah

IPC: G06T15/00 ,  G06T1/20 ,  G06F11/30

Abstract: The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine a state for each graphics state group of a plurality of graphics state groups. Further, aspects of the present disclosure can determine whether at least one graphics state group of the plurality of graphics state groups includes a changed state. Additionally, aspects of the present disclosure can communicate state information for the at least one graphics state group when the at least one graphics state group includes a changed state. In some aspects, the state information includes information regarding the state of the at least one graphics state group. Aspects of the present disclosure can also configure a draw state for the plurality of graphics state groups, where the draw state includes state information for each of the graphics state groups.

公开(公告)号：US09836810B2

公开(公告)日：2017-12-05

申请号：US15012467

申请日：2016-02-01

Applicant: QUALCOMM Incorporated

Inventor： Murat Balci ,  Christopher Paul Frascati ,  Avinash Seetharamaiah

IPC: G06T1/20 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06T15/005

Abstract: The present disclosure provides systems and methods for multi-path rendering on tile based architectures including executing, with a graphics processing unit (GPU), a query pass, executing, with the GPU, a condition true pass based on the query pass without executing a flush operation, executing, with the GPU, a condition false pass based on the query pass without executing a flush operation, and responsive to executing the condition true pass and the condition false pass, executing, with the GPU, a flush operation.