公开(公告)号：US11361944B2

公开(公告)日：2022-06-14

申请号：US17114679

申请日：2020-12-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/3065 ,  H01J37/32 ,  H01J37/18

Abstract: A plasma processing method, including: a trenched substrate preparation process of preparing a trenched substrate having trenches having a bottom exposing an oxide film; and an oxide film removal process of exposing the trenched substrate to a plasma, to remove the oxide film. The oxide film removal process includes a plurality of cycles, each cycle including: an oxide film etching step of etching the oxide film; and a cleaning step of removing an attached matter on inner walls of the trenches, after the oxide film etching step.

公开(公告)号：US11289428B2

公开(公告)日：2022-03-29

申请号：US16872801

申请日：2020-05-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Kiyoshi Arita ,  Shogo Okita ,  Hidehiko Karasaki

IPC: H01L21/00 ,  H01L23/544 ,  H01L21/66 ,  H01L21/268 ,  H01L21/78 ,  B23K26/57 ,  B23K26/18 ,  B23K26/351 ,  B23K26/0622 ,  B23K103/00 ,  B23K101/40

Abstract: An element chip manufacturing method including: preparing a semiconductor substrate including a first layer having a first principal surface, and a second layer having a second principal surface, the first layer provided with element regions, a dicing region, and an alignment mark, wherein the first layer includes a semiconductor layer, and the second layer includes a metal layer adjacent to the semiconductor layer; irradiating a first laser beam absorbed in the metal film and passing through the semiconductor layer, from the second principal surface side to a first region corresponding to the mark; imaging the semiconductor substrate from the second principal surface side with a camera, and then calculating a second region corresponding to the dicing region on the second principal surface; irradiating a second laser beam to the second region from the second principal surface side; and dicing the semiconductor substrate into a plurality of element chips.

公开(公告)号：US11145548B2

公开(公告)日：2021-10-12

申请号：US16362933

申请日：2019-03-25

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidefumi Saeki ,  Atsushi Harikai ,  Shogo Okita

IPC: H01L21/78 ,  H01L23/544 ,  H01L21/268 ,  B23K26/00 ,  B23K26/364 ,  H01L21/3065

Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.

公开(公告)号：US11101112B2

公开(公告)日：2021-08-24

申请号：US16114467

申请日：2018-08-28

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita

IPC: H01J37/32 ,  H01L21/683 ,  H01L21/677 ,  H01L21/78 ,  H01L21/67

Abstract: A plasma processing device has a chamber that can be depressurized, a plasma source to generate plasma in the chamber, a stage in the chamber on which the conveyance carrier is placed, and a cover on the stage to cover a holding sheet and a frame and including a window portion penetrating a thickness direction. The cover includes an introduction port, a discharge port, and a coolant flow path connecting the introduction port and the discharge port and not overlapping with a region on an inner side of the frame in plan view. The stage includes a supply port communicated with the introduction port to allow supply of coolant to the coolant flow path when the cover is on the stage, and a recovery port communicated with the discharge port to allow recovery of coolant supplied to the coolant flow path when the cover is on the stage.

公开(公告)号：US10964597B2

公开(公告)日：2021-03-30

申请号：US16567047

申请日：2019-09-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Noriyuki Matsubara ,  Hidefumi Saeki ,  Akihiro Itou

IPC: H01L21/78 ,  H01L21/68 ,  H01L21/683

Abstract: An element chip manufacturing method including: a preparing step of preparing a first conveying carrier including a holding sheet and a frame, and a substrate held on the holding sheet, the holding sheet having a first surface and a second surface opposite the first surface, the frame attached to at least part of a peripheral edge of the holding sheet; a placing step of placing the first conveying carrier holding the substrate, on a second conveying carrier; a preprocessing step of preprocessing the substrate, after the placing step; a removing step of removing the second conveying carrier, after the preprocessing step; and a dicing step of subjecting the substrate held on the first conveying carrier to plasma exposure, after the removing step, to form a plurality of element chips from the substrate.

公开(公告)号：US10923357B2

公开(公告)日：2021-02-16

申请号：US15899422

申请日：2018-02-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Akihiro Itou ,  Atsushi Harikai ,  Noriyuki Matsubara ,  Shogo Okita

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/687 ,  H01L21/683 ,  H01L21/78 ,  H01L21/311 ,  H01L21/67

Abstract: Provided is a manufacturing process of an element chip, which comprises a preparation step, a setting step for setting the substrate on a stage, and a plasma-dicing step for dividing the substrate into a plurality of element chips, wherein the plasma-dicing step is achieved by repeatedly implementing etching routines each including an etching step for etching the second layer along the street regions to form a plurality of grooves and a depositing step for depositing a protective film on inner walls of the grooves, wherein the plasma-dicing step includes a first etching step for forming the grooves each having a first scallop on the inner wall thereof at a first pitch, and a second etching step for forming the grooves each having a second scallop on the inner wall thereof at a second pitch, and wherein the second pitch is greater than the first pitch.

公开(公告)号：US10892190B2

公开(公告)日：2021-01-12

申请号：US16246627

申请日：2019-01-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Atsushi Harikai ,  Noriyuki Matsubara ,  Hidefumi Saeki ,  Akihiro Itou

IPC: H01L21/78 ,  H01L21/56 ,  H01L21/683 ,  H01L21/3065 ,  H01J37/00 ,  H01L21/311 ,  H01L21/687 ,  H01L21/67

Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including dicing regions and element regions, attaching a holding sheet held on a frame with a die attach film in between, forming a protective film covering the substrate, forming a plurality of grooves in the protective film along the dicing regions, plasma-etching the substrate to expose the die attach film and then die attach film along the dicing regions, and picking up each of the element chips along with the separated die attach film away from the holding sheet, wherein the die attach film has an area greater than that of the substrate, and wherein the protective film includes a first covering portion covering the substrate and a second covering portion covering at least a portion of the die attach film that extends beyond an outer edge of the substrate.

公开(公告)号：US10714356B2

公开(公告)日：2020-07-14

申请号：US16154930

申请日：2018-10-09

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Atsushi Harikai ,  Akihiro Itou ,  Noriyuki Matsubara

IPC: H01L21/306 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/683 ,  H01L21/677 ,  H01L21/687 ,  H01L21/311 ,  H01J37/00

Abstract: Provided is a plasma processing method which comprises steps of preparing a conveying carrier including a holding sheet and a frame provided on a peripheral region of the holding sheet, adhering the substrate on the holding sheet in an inner region inside the peripheral region to hold the substrate on the conveying carrier, sagging the holding sheet in the inner region, setting the conveying carrier on a stage provided within a plasma processing apparatus to contact the holding sheet on the stage so that the holding sheet in the inner region touches the stage before the holding sheet in the peripheral region does, and plasma processing the substrate.

公开(公告)号：US10297489B2

公开(公告)日：2019-05-21

申请号：US15427590

申请日：2017-02-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Atsushi Harikai ,  Akihiro Itou

IPC: H01L21/67 ,  H01L21/687 ,  H01L21/3065 ,  H01J37/32

Abstract: A plasma processing method includes a mounting process of mounting a holding sheet holding a substrate in a stage provided in a plasma processing apparatus, and a fixing process of fixing the holding sheet to the stage. The plasma processing method further includes a determining process of determining whether or not a contact state of the holding sheet with the stage is good or bad after the fixing process, and a plasma etching process of etching the substrate by exposing a surface of the substrate to plasma on the stage, in a case in which the contact state is determined to be good in the determining process.

公开(公告)号：US10217617B2

公开(公告)日：2019-02-26

申请号：US14525712

申请日：2014-10-28

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita

IPC: H01J37/32 ,  H01L21/67 ,  H01L21/78 ,  H01L21/683

Abstract: A dry etching apparatus plasma processes a wafer held by a carrier having a frame and a holding sheet. An electrode unit of a stage includes an electrostatic chuck. An area of an upper surface of the electrostatic chuck onto which the wafer is placed via the holding sheet is a flat portion and is not subject to backside gas cooling. A first groove structure is formed in the area onto which the wafer is placed via the holding sheet as well as in an area onto which a holding sheet between the wafer and the frame is placed. To a minute space defined by the first groove structure and the carrier, a heat transfer gas is supplied from a first heat transfer gas supply section through a heat transfer gas supply hole (backside gas cooling).