公开(公告)号：US10108490B1

公开(公告)日：2018-10-23

申请号：US15604661

申请日：2017-05-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Hsiang Lin ,  Shao-Wei Yen ,  Cheng-Che Yang ,  Kuo-Hsin Lai

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: A decoding method, a memory storage device and a memory control circuit unit. The method includes: reading a plurality of bits from a plurality of first memory cells; performing a first decoding operation on the bits according to first reliability information; and performing a second decoding operation on the bits according to second reliability information if the first decoding operation fails and meets a default condition, and the second reliability information is different from the first reliability information, and a correction ability of the second reliability information for a first type error of the bits is higher than a correction ability of the first reliability information for the first type error. In addition, the first type error is generated by performing a specific programming operation on the first memory cells based on error data.